Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines最新文献_第4页

TCP-Stream reassembly and state tracking in hardware 硬件中的tcp流重组和状态跟踪

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106687

M. Necker, Didier Contis, D. Schimmel

引用次数: 42

RACER - a rapid prototyping accelerator for pulsed neural networks RACER -脉冲神经网络的快速原型加速器

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106683

Cyprian Grassmann, J. Anlauf

引用次数: 3

Automatic latency-optimal design of FPGA-based systolic arrays 基于fpga的收缩阵列自动延迟优化设计

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106692

J. Nash

{"title":"Automatic latency-optimal design of FPGA-based systolic arrays","authors":"J. Nash","doi":"10.1109/FPGA.2002.1106692","DOIUrl":"https://doi.org/10.1109/FPGA.2002.1106692","url":null,"abstract":"\"Systolic\" algorithms have been shown to be suitable for a very large range of structured problems (i.e., linear algebra, graph theory, computational geometry, number-theoretic algorithms, string matching, sorting/searching, dynamic programming, discreet mathematics). Usage of this systolic architecture class has not been widespread in the past, in part because programmable hardware that supported this computing paradigm was not cost-effective to build and no design tools existed. However, suitable hardware has begun to appear. Complex FPGAs now provide an adequate level of speed, density and programmability in the form of reconfigurable computers, boards, and chips with embedded computational support. Such hardware could allow rapid implementation and change of systolic algorithms leading to inexpensive \"programmable\" systolic array hardware. Furthermore, the architectural characteristics of much FPGA hardware matches that required by systolic processing, because this technology is constructed from tiling identical memory and logic blocks along with supporting mesh interconnection networks. The symbolic parallel algorithm development environment (SPADE) described here is being developed to allow a designer to easily and rapidly explore the design space of various systolic algorithm implementations so that FPGA system tradeoffs can be efficiently analyzed. The intention is to allow a user to specify his algorithm with traditional high-level code, set some architectural constraints and then view the results in a meaningful graphical format.","PeriodicalId":272235,"journal":{"name":"Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116978078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Analysis and implementation of the discrete element method using a dedicated highly parallel architecture in reconfigurable computing 可重构计算中离散元方法的高度并行分析与实现

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106672

Benjamin Carrión Schäfer, S. Quigley, A. Chan

引用次数: 12

Module generators driving the compilation for adaptive computing systems 模块生成器驱动自适应计算系统的编译

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106689

A. Koch, Nico Kasprzyk

引用次数: 2

On implementing a configware/software SAT solver 实现一个组态/软件SAT求解器

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106685

N. A. Reis, J. Sousa

引用次数: 13

Queue machines: hardware compilation in hardware 队列机:硬件中的硬件编译

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106670

H. Schmit, B. Levine, Benjamin Ylvisaker

引用次数: 44

An FPGA implementation of triangle mesh decompression 三角网格解压缩的FPGA实现

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106658

T. Mitra, T. Chiueh

引用次数: 18

FPGA-based template matching using distance transforms 基于fpga的模板匹配，使用距离变换

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106664

Stefan Hezel, A. Kugel, R. Männer, D. Gavrila

引用次数: 45

A massively parallel RC4 key search engine 一个大规模并行RC4密钥搜索引擎

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106657

K. H. Tsoi, Kin-Hong Lee, P. Leong

引用次数: 52