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Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines最新文献

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System-level modelling and implementation technique for run-time reconfigurable systems 运行时可重构系统的系统级建模和实现技术
Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106690
T. Rissa, M. Vasilko, J. Niittylahti
{"title":"System-level modelling and implementation technique for run-time reconfigurable systems","authors":"T. Rissa, M. Vasilko, J. Niittylahti","doi":"10.1109/FPGA.2002.1106690","DOIUrl":"https://doi.org/10.1109/FPGA.2002.1106690","url":null,"abstract":"This paper presents a system-level approach for modelling and implementing hardware-software systems, which contain Run-Time Reconfigurable (RTR) hardware. The developed technique provides management and scheduling of RTR tasks from system-level simulations to synthesizable VHDL descriptions. The developed technique was implemented using OCAPI-xl - a system-level modelling and implementation tool based on C + + libraries. The proposed approach allows designers to explore the tradeoffs between implementation of system partitions in software, static hardware, and RTR hardware. After the system has been partitioned, an OCAPI-xl-based design flow can be utilized for implementation of all the system components.","PeriodicalId":272235,"journal":{"name":"Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114190376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
On sparse matrix-vector multiplication with FPGA-based system 基于fpga的稀疏矩阵-向量乘法系统
Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106681
H. ElGindy, Yen-Liang Shue
{"title":"On sparse matrix-vector multiplication with FPGA-based system","authors":"H. ElGindy, Yen-Liang Shue","doi":"10.1109/FPGA.2002.1106681","DOIUrl":"https://doi.org/10.1109/FPGA.2002.1106681","url":null,"abstract":"In this paper we report on our experimentation with the use of FPGA-based system to solve the irregular computation problem of evaluating y = Ax when the matrix A is sparse. The main features of our matrix-vector multiplication algorithm are (i) an organization of the operations to suit the FPGA-based system ability in processing a stream of data, and (ii) the use of distributed arithmetic technique together with an efficient scheduling heuristic to exploit the inherent parallelism in the matrix-vector multiplication problem. The performance of our algorithm has been evaluated with an implementation on the Pamette FPGA-based system.","PeriodicalId":272235,"journal":{"name":"Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132407860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Mobile Memory: Improving memory locality in very large reconfigurable fabrics 移动存储器:在非常大的可重构结构中改进存储器局部性
Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106674
Rong Yan, S. Goldstein
{"title":"Mobile Memory: Improving memory locality in very large reconfigurable fabrics","authors":"Rong Yan, S. Goldstein","doi":"10.1109/FPGA.2002.1106674","DOIUrl":"https://doi.org/10.1109/FPGA.2002.1106674","url":null,"abstract":"As the size of reconfigurable fabrics increases we can envision entire applications being mapped to a reconfigurable device; not just the code, but also the memory. These larger circuits, unfortunately, will suffer from the problem of a growing memory bottleneck. In this paper we explore how mobile memory techniques, inspired by cache-only memory architectures, can be applied to help solve this problem. The basic idea is to move the memory to the location of the accessor. Using both an analytical model and simulation we investigate several different memory movement algorithms. The results show that mobility can, on average, decrease memory latency 2x; which translates into speedup of about 15%.","PeriodicalId":272235,"journal":{"name":"Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129607798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fast and guaranteed C compilation onto the PACT-XPP/spl trade/ reconfigurable computing platform 快速和有保证的C编译到PACT-XPP/spl交易/可重构计算平台
Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-04-22 DOI: 10.1109/FPGA.2002.1106688
João MP Cardoso, M. Weinhardt
{"title":"Fast and guaranteed C compilation onto the PACT-XPP/spl trade/ reconfigurable computing platform","authors":"João MP Cardoso, M. Weinhardt","doi":"10.1109/FPGA.2002.1106688","DOIUrl":"https://doi.org/10.1109/FPGA.2002.1106688","url":null,"abstract":"We introduce the XPP-VC high-level compiler, which maps C programs to the coarse-grained XPP architecture. XPP-VC's main feature is the integration of pipeline vectorization and temporal partitioning techniques. The former provides high-throughput inner loop computations and the later allows the compilation of large programs or the use of fewer XPP processing elements. Although the preliminary results are very encouraging, improvements on the generation of configurations are still required. The evaluation we have conducted shows that only a few seconds are required to generate, from algorithms in C, the binaries to program the XPP. To our knowledge this compilation performance is unmatched by any other compiler targeting reconfigurable architectures. Moreover the compiler still achieves high-performance implementations. Since the XPP is delivered as an IP core or device to be coupled to a host processor, a future version of XPP-VC will consider co-compilation, i.e., compilation to hybrid microprocessor/XPP architectures.","PeriodicalId":272235,"journal":{"name":"Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126800367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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