Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines最新文献_第3页

Mapping multi-mode circuits to LUT-based FPGA using embedded MUXes 使用嵌入式mux将多模电路映射到基于lut的FPGA

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106699

T. Courtney, R. Turner, Roger Francis Woods

引用次数: 5

Coarse-grain pipelining on multiple FPGA architectures 多FPGA架构上的粗粒度流水线

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106663

H. Ziegler, Byoungro So, Mary W. Hall, P. Diniz

{"title":"Coarse-grain pipelining on multiple FPGA architectures","authors":"H. Ziegler, Byoungro So, Mary W. Hall, P. Diniz","doi":"10.1109/FPGA.2002.1106663","DOIUrl":"https://doi.org/10.1109/FPGA.2002.1106663","url":null,"abstract":"Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer performance advantages for application domains such as image processing, where the use of customized pipelines exploits the inherent coarse-grain parallelism. In this paper we describe a set of program analyses and an implementation that map a sequential and un-annotated C program into a pipelined implementation running on a set of FPGAs, each with multiple external memories. Based on well-known parallel computing analysis techniques, our algorithms perform unrolling for operator parallelization, reuse and data layout for memory parallelization and precise communication analysis. We extend these techniques for FPGA-based systems to automatically partition the application data and computation into custom pipeline stages, taking into account the available FPGA and interconnect resources. We illustrate the analysis components by way of an example, a machine vision program. We present the algorithm results, derived with minimal manual intervention, which demonstrate the potential of this approach for automatically deriving pipelined designs from high-level sequential specifications.","PeriodicalId":272235,"journal":{"name":"Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129461865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 43

Using on-chip configurable logic to reduce embedded system software energy 采用片上可配置逻辑，降低嵌入式系统软件能耗

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106669

G. Stitt, Brian Grattan, J. Villarreal, F. Vahid

{"title":"Using on-chip configurable logic to reduce embedded system software energy","authors":"G. Stitt, Brian Grattan, J. Villarreal, F. Vahid","doi":"10.1109/FPGA.2002.1106669","DOIUrl":"https://doi.org/10.1109/FPGA.2002.1106669","url":null,"abstract":"We examine the energy savings possible by re-mapping critical software loops from a microprocessor to configurable logic appearing on the same-chip in commodity chips now commercially available. That logic is typically intended to implement peripherals and coprocessors without increasing chip count-but we show that reduced software energy is an additional benefit, making such chips even more useful. We find critical software loops and re-implement them in the configurable logic such that a repeating software task completes sooner, allowing us to put the system in a low-power state for longer periods, thus reducing energy. We use simulations and estimations for a hypothetical device having a 32-bit MIPS processor plus configurable logic, yielding energy savings of 25%, increasing to 39% assuming voltage scaling. We physically measured several examples running on two commercial single-chip devices having an 8-bit 8051 microprocessor plus configurable logic and a 32-bit ARM microprocessor with configurable logic, with energy savings of 71% and 53% respectively, increasing to an estimated 89% and 75% assuming voltage scaling.","PeriodicalId":272235,"journal":{"name":"Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129799462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 42

Custom computing machines for the set covering problem 为集合覆盖问题定制计算机器

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106671

Christian Plessl, M. Platzner

引用次数: 9

The design of the Amalgam reconfigurable cluster 汞合金可重构集群的设计

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106696

Joshua D. Walstrom, Jeffrey J. Cook, Derek B. Gottlieb, Steve Ferrera, Chi-Wei Wang, N. Carter

引用次数: 5

A scalable FPGA-based custom computing machine for a medical image processing 一种可扩展的基于fpga的医学图像处理定制计算机

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106695

T. Yokota, Masamichi Nagafuchi, Y. Mekada, T. Yoshinaga, K. Ootsu, T. Baba

引用次数: 13

Accelerating radiosity calculations using reconfigurable platforms 使用可重构平台加速辐射计算

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106684

Henry Styles, W. Luk

引用次数: 10

Using floating-point arithmetic on FPGAs to accelerate scientific N-Body simulations 在fpga上使用浮点运算加速科学n体仿真

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106673

G. Lienhart, A. Kugel, R. Männer

引用次数: 99

Hyperspectral image compression on reconfigurable platforms 可重构平台上的高光谱图像压缩

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106679

T. W. Fry, S. Hauck

引用次数: 57

Single-chip gigabit mixed-version IP router on Virtex-II Pro Virtex-II Pro上的单芯片千兆混合版本IP路由器

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2002-09-22 DOI: 10.1109/FPGA.2002.1106659

G. Brebner

{"title":"Single-chip gigabit mixed-version IP router on Virtex-II Pro","authors":"G. Brebner","doi":"10.1109/FPGA.2002.1106659","DOIUrl":"https://doi.org/10.1109/FPGA.2002.1106659","url":null,"abstract":"This paper concerns novel single-chip system architecture options, based on the Xilinx Virtex-II Pro part, which includes up to four PowerPC cores and was launched in Spring 2002. The research described here was carried out pre-launch (i.e., prior to availability of real parts), so the paper focuses on initial architectural experiments based on simulation. The application is a Mixed-version IP Router, named MIR, servicing gigabit ethernet ports. This would be of use to organizations with several gigabit ethernets, with a mixture of IPv4 and IPv6 hosts and routers attached directly to the networks. A particular benefit of a programmable approach based on Virtex-II Pro is that the router's functions can evolve smoothly, maintaining router performance as the organization migrates from IPv4 to IPv6 internally, and also as the Internet migrates externally. The basic aim is to carry out more frequent, and less control intensive, functions in logic, and other functions in the processor. Two prototypes are described here. Both support four ethernet ports, but the designs are scalable upwards. The second one, the more ambitious of the two, instantiates a configuration appropriate when the bulk of the incoming packets are IPv4. Such packets are processed and switched entirely by logic, with no internal copying of packets between buffers and virtually no delay between packet receipt and onward forwarding. This involves a specially-tailored internal interconnection network between the four ports, and also processing performed in parallel with packet receipt, i.e. multi-threading in logic. IPv6 packets, or some rare IPv4 cases, are passed to a PowerPC core for processing. In essence, the PowerPC acts as a slave to the logic, rather than the more common opposite master-slave relationship.","PeriodicalId":272235,"journal":{"name":"Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115344130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22