2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献_第3页

High-Throughput and Low-Power Architectures for the AV1 Arithmetic Encoder AV1算法编码器的高吞吐量和低功耗架构

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529994

Tulio Pereira Bitencourt, Fábio Luís Livi Ramos, S. Bampi

引用次数: 5

Exploration of a Low-power CMOS Voltage Squarer 一种低功耗CMOS电压平方器的研制

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9530000

V. O. Costa, A. Aita, Adilson J. Cardoso, C. Rodrigues, Jefferson Luiz B. Marques

引用次数: 1

Edge Verification: Ensuring Correctness under Resource Constraints 边缘验证:保证资源约束下的正确性

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529977

R. Drechsler, Caroline Dominik

引用次数: 18

A 237 ppm/°C L-Band Active Inductance Based Voltage Controlled Oscillator in SOI 0.18 µm 一个237 ppm/°C l波段有源电感基于电压控制振荡器在SOI 0.18µm

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529990

J. R. O. R. Martins, F. Alves, Pietro M. Ferreira

引用次数: 1

Optimizing a Robust Miller OTA Implemented with Diamond Layout Style for MOSFETs By Using iMTGSPICE 通过使用iMTGSPICE优化具有菱形布局风格的mosfet的鲁棒米勒OTA

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529991

José Roberto Banin Júnior, R. A. de Lima Moreto, G. A. da Silva, C. Thomaz, S. Gimenez

{"title":"Optimizing a Robust Miller OTA Implemented with Diamond Layout Style for MOSFETs By Using iMTGSPICE","authors":"José Roberto Banin Júnior, R. A. de Lima Moreto, G. A. da Silva, C. Thomaz, S. Gimenez","doi":"10.1109/SBCCI53441.2021.9529991","DOIUrl":"https://doi.org/10.1109/SBCCI53441.2021.9529991","url":null,"abstract":"This paper describes an innovative methodology to design and optimize robust analog Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) with Diamond layout style (hexagonal gate shape) for Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), focusing on reducing their die areas and improving their electrical performances. The Miller CMOS Operational Transconductance Amplifier (OTA) is used to validate this design and optimization approach by using a computational tool, which integrates the human intelligence (expertise of the designer) and the artificial intelligence (use an evolutionary optimization algorithm to search robust potential solutions quickly and accurately). The 180 nm CMOS ICs technology node was considered in this work. The Longitudinal Corner Effect (LCE) and Parallel Connections of MOSFETs with different channel Lengths Effect (PAMDLE) present in the Diamond MOSFET structure are analytically modeled to be simulated in the SPICE. In addition, the iMTGSPICE computation tool was improved with a new feature to automatically convert Conventional MOSFETs (CMs) into Diamond MOSFETs (DMs). The main results show that the Miller CMOS OTA implemented with DMs (ɑ= 45°) can reduce up to 43% of their die area, practically without impairing the design specifications and robustness (Corner and Monte Carlo Analyses) in comparison to the one implemented with CM counterparts. Furthermore, these results were obtained quickly, i.e., approximately 4 hours to obtain five different robust potential solutions available to the designer.","PeriodicalId":270661,"journal":{"name":"2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130590650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Injection-Locked Ring Oscillator based Phase-Lacked-Loop for 1.6 Gbps Clock Recovery 基于注入锁环振荡器的1.6 Gbps时钟恢复缺相环

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529969

D. Vert, J. Bégueret, M. Pignol, F. Malou, V. Lebre, E. Moutaye

引用次数: 0

A Robust and Power-Efficient Power Line Interference Canceling VLSI Design 一种鲁棒且节能的电力线干扰消除VLSI设计

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529983

M. D. da Rosa, P. D. da Costa, E. D. da Costa, S. Almeida, Guilherme Paim, S. Bampi

{"title":"A Robust and Power-Efficient Power Line Interference Canceling VLSI Design","authors":"M. D. da Rosa, P. D. da Costa, E. D. da Costa, S. Almeida, Guilherme Paim, S. Bampi","doi":"10.1109/SBCCI53441.2021.9529983","DOIUrl":"https://doi.org/10.1109/SBCCI53441.2021.9529983","url":null,"abstract":"The electric generators functional performance is prone to suffer from harmonic distortions such as first, second, and third-order. This work proposes a low power dissipation VLSI hardware architecture for a robust power line interference canceling (PLIC). Our proposed Least Mean Square (LMS) architecture has just four clock cycles of latency per sample. The Harmonic Generator (HG) architectures are exploited and optimized in their arithmetic operations. We substituted conventional multiplier by adders and shifters, and used efficient and previously published squared multipliers. In particular, the Vedic multiplier architecture is proven to be an efficient alternative for use in the HG. Our VLSI synthesis results show that the proposed approach, combining the optimized adaptive filters LMS and HG's hardware architecture, turns the PLIC VLSI structure robust and power-efficient by effectively suppressing interferences in both ECG (Electrocardiogram) and EEG (Electroencephalo-gram) signals. Notably, the PLIC architecture is more efficient in the circuit area and power dissipation with the Vedic multiplier in the HG, with savings of up to 40% in total power and 15% in VLSI area, compared to the state-of-the-art solution.","PeriodicalId":270661,"journal":{"name":"2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114826742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

High-Performance Design for the AV1 Multi - Alphabet Arithmetic Decoder AV1多字母算术解码器的高性能设计

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529970

Jiovana Sousa Gomes, Fábio Luís Livi Ramos

{"title":"High-Performance Design for the AV1 Multi - Alphabet Arithmetic Decoder","authors":"Jiovana Sousa Gomes, Fábio Luís Livi Ramos","doi":"10.1109/SBCCI53441.2021.9529970","DOIUrl":"https://doi.org/10.1109/SBCCI53441.2021.9529970","url":null,"abstract":"In the course of the last years, there has been increasing use of video streams over the Internet. Streaming videos over networks is expensive, as it takes finite resources and physical infrastructure. Hence, companies have been investing in new standards for video encoding with higher compression rates. The AV1 video encoding format was launched in 2018 by the Alliance for Open Media as an open-source and royalty-free format. This paper presents a hardware architecture named Multi-Alphabet Arithmetic Decoder (MaAD) for the first step of the decoder: the entropy decoding, more specifically, its kernel step, the arithmetic decoding block. AV1 uses a multi-alphabet approach of up to sixteen symbols, where the majority of them have different and dynamic probabilities of occurrence. The architecture was synthesized to ST 65nm library, requiring 34.3K gates, and achieved the frequency of 467MHz, with an estimated throughput of 766 Mbits/s, capable of 8K video processing at 60 frames per second. To the best of the authors' knowledge, MaAD is the first-ever academic design with detailed implementation targeting the AV1 arithmetic decoding step.","PeriodicalId":270661,"journal":{"name":"2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130344446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Novel Three-Input Gates for Silicon Quantum Dot 新型硅量子点三输入门

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9530002

Maria D. Vieira, Ícaro G. S. Moreira, P. A. Silva, L. O. Luz, R. Ferreira, O. P. V. Neto, J. Nacif

引用次数: 6

34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design [Front matter] 第34届SBC/SBMicro/IEEE/ACM集成电路与系统设计研讨会

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/sbcci53441.2021.9529995

引用次数: 0