一种低功耗CMOS电压平方器的研制

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI:10.1109/SBCCI53441.2021.9530000

V. O. Costa, A. Aita, Adilson J. Cardoso, C. Rodrigues, Jefferson Luiz B. Marques

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引用次数: 1

摘要

本文讨论了一种电压倍增器，并探讨了其作为电压平方器的用途，目的是减少功耗和面积。所提出的电路可以在250kHz上以-30.4的最大增益工作。这些数据还显示，在VDD= 1.8 V时，总功耗约为501 nW。为了减少平方灵敏度的过程变化过角，偏置电路也敏感的这些变化被用来减轻这种影响。利用标准0.18 μ m CMOS工艺的晶体管模型进行了布局前和布局后仿真，验证了这一点。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Exploration of a Low-power CMOS Voltage Squarer

This paper addresses a reported voltage multiplier and explores its use as a voltage squarer with the aim of reducing the power consumption and area. The proposed circuit can operate with a maximum gain of -30.4 up 250kHz. These ones have also shown the total power consumption is about 501 nW at VDD= 1.8 V. In order to reduce the squarer sensitivity to process variations over corners, a bias circuit also sensitive to these variations was used to mitigate such effects. This was verified by pre- and post-layout simulations using transistor's models of standard 0.18 µ m CMOS process.

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2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)

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