2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献_第2页

Configurable Approximate Hardware Accelerator to Compute SATD and SAD Metrics for Low Power All-Intra High Efficiency Video Coding 可配置的近似硬件加速器计算SATD和SAD指标，用于低功耗全内高效率视频编码

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529974

Victor H. S. Lima, Matheus F. Stigger, L. Soares, C. Diniz, S. Bampi

{"title":"Configurable Approximate Hardware Accelerator to Compute SATD and SAD Metrics for Low Power All-Intra High Efficiency Video Coding","authors":"Victor H. S. Lima, Matheus F. Stigger, L. Soares, C. Diniz, S. Bampi","doi":"10.1109/SBCCI53441.2021.9529974","DOIUrl":"https://doi.org/10.1109/SBCCI53441.2021.9529974","url":null,"abstract":"Connecting billions of network cameras to the cloud is a challenge that heavily taxes the network bandwidth for video transmissions. High Efficiency Video Coding (HEVC) standard offers a good option from the bit-rate reduction and video quality perspectives, but it is more computational complex than previous standards. This paper uses HEVC All-Intra configuration in this context, thus simplifying video encoding by avoiding interframe prediction, and by using VLSI hardware acceleration and approximate computing. Sum of Absolute Transformed Differences (SATD) is a distortion metric used in intra-mode decision fast algorithm and consumes a significant part of intra-frame encoding execution time in software. This work proposes a configurable-approximate hardware accelerator supporting 8 × 8 SATD, the simpler Sum of Absolute Differences (SAD) metric, and two approximate SATD versions by excluding columns of arithmetic operators of the 8 × 8 Hadamard Transform. When operating in three-columns exclusion, five-columns exclusion, and SAD configurations, the total VLSI power dissipation is reduced by 19.87%, 32.33% and 39.16% respectively, when compared to precise SATD computation.","PeriodicalId":270661,"journal":{"name":"2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129130926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Exploring Approximate Computing and Near- Threshold Operation to Design Energy -efficient Multipliers 探索近似计算和近阈值运算设计节能乘法器

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529347

Vinicius Zanandrea, Douglas M. Borges, V. S. Rosa, C. Meinhardt

引用次数: 3

A 0.6 V, 3.3 nW, Adjustable Gaussian Circuit for Tunable Kernel Functions 一个0.6 V, 3.3 nW，可调高斯电路可调谐核函数

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529988

Vassilis Alimisis, Marios Gourdouparis, Christos Dimas, P. Sotiriadis

引用次数: 9

Artificial Neural Network Based Automatic Modulation Classification System Applied to FPGA 基于人工神经网络的FPGA自动调制分类系统

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529976

Adenilson F. De Castro, Ronny S. R. Milléo, L. Lolis, A. Mariano

引用次数: 0

MUTECO: A Framework for Collaborative Allocation in CPU-FPGA Multi-tenant Environments MUTECO: CPU-FPGA多租户环境下的协同分配框架

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529992

M. Jordan, Guilherme Korol, M. B. Rutzig, A. C. S. Beck

{"title":"MUTECO: A Framework for Collaborative Allocation in CPU-FPGA Multi-tenant Environments","authors":"M. Jordan, Guilherme Korol, M. B. Rutzig, A. C. S. Beck","doi":"10.1109/SBCCI53441.2021.9529992","DOIUrl":"https://doi.org/10.1109/SBCCI53441.2021.9529992","url":null,"abstract":"CPU-FPGA collaborative environments are progressively being adopted by Cloud Warehouses. In this environment, multiple clients share the same infrastructure to maximize resource utilization with energy efficiency and scalability. However, such a provisioning of resources is challenging, since kernels may be concurrently assigned to both CPU and FPGA in a scenario where available resources and workload characteristics drastically vary. To make the best use of resources in this complex environment, we propose MUTECO: A MUlti-TEnant COllaborative resource provisioning framework. MUTECO optimizes considering both multitenancy and CPU-FPGA collaborative execution, in contrast to existing approaches that focus on collaborative single-tenant or non-collaborative multi-tenant workloads. MUTECO is highly configurable and integrated to the Hypervisor layer, so it can be tuned to optimize convergence time, performance, and energy, according to different scenarios that comprise number of tenant requests, the incoming kernels' behavior, and the available resources. Over a varied set of scenarios, MUTECO outperforms in up to 2.91x and 2.39x the current non-collaborative and single-tenant approaches.","PeriodicalId":270661,"journal":{"name":"2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129773828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Soft Error Tolerant Quasi-Delay Insensitive Asynchronous Circuits: Advancements and Challenges 软容错准延迟不敏感异步电路:进展与挑战

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9530001

Ashiq A. Sakib

引用次数: 4

ETCG: Energy-Aware CPU Thread Throttling for CPU-GPU Collaborative Environments ETCG:用于CPU- gpu协作环境的能量感知CPU线程节流

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529986

Tiago Knorst, M. Jordan, Arthur F. Lorenzen, M. B. Rutzig, Antonio Carlos Schneider Beck

{"title":"ETCG: Energy-Aware CPU Thread Throttling for CPU-GPU Collaborative Environments","authors":"Tiago Knorst, M. Jordan, Arthur F. Lorenzen, M. B. Rutzig, Antonio Carlos Schneider Beck","doi":"10.1109/SBCCI53441.2021.9529986","DOIUrl":"https://doi.org/10.1109/SBCCI53441.2021.9529986","url":null,"abstract":"High-Performance computing systems have been constantly adopting CPU-GPU architectures as a collaborative environment to accelerate applications by partitioning threads/kernels execution across both devices. However, exploiting the synergetic benefits of this system is challenging, since maximizing resource utilization by triggering the highest number threads is not always the best strategy to optimize performance or energy consumption. This work shows that selecting the right number of CPU threads in a CPU-GPU collaborative environment is even trickier. To address this problem, we propose ETCG - Energy-aware CPU Thread throttling for CPU-GPU collaborative environments. ETCG transparently selects a near-optimal number of CPU threads to minimize the energy-delay product (EDP) of CPU-GPU applications. Compared to the use of the maximum number of threads supported by the hardware, ETCG provides, on average, 73% of EDP reduction. In addition, ETCG shows, on average, 3% less EDP by just taking 5% of searching time compared to the optimal solution.","PeriodicalId":270661,"journal":{"name":"2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126403367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Accuracy and Size Trade-off of a Cartesian Genetic Programming Flow for Logic Optimization 逻辑优化中笛卡尔遗传规划流的精度和尺寸权衡

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529968

A. Berndt, I. S. Campos, B. Lima, M. Grellert, J. T. Carvalho, C. Meinhardt, B. A. de Abreu

{"title":"Accuracy and Size Trade-off of a Cartesian Genetic Programming Flow for Logic Optimization","authors":"A. Berndt, I. S. Campos, B. Lima, M. Grellert, J. T. Carvalho, C. Meinhardt, B. A. de Abreu","doi":"10.1109/SBCCI53441.2021.9529968","DOIUrl":"https://doi.org/10.1109/SBCCI53441.2021.9529968","url":null,"abstract":"Logic synthesis tools face tough challenges when providing algorithms for synthesizing circuits with increased inputs and complexity. Traditional approaches for logic synthesis have been in the spotlight so far. However, due to advances in machine learning and their high performance in solving specific problems, such algorithms appear as an attractive option to improve electronic design tools. In our work, we explore Cartesian Genetic Programming for logic optimization of exact or approximate combinational circuits. The proposed CGP flow receives input from the circuit description in the format of AND-Inverter Graphs and its expected behavior as a truth-table. The CGP may improve solutions found by other techniques used for bootstrapping the evolutionary process or initialize the search from random (unbiased) individuals seeking optimal circuits. We propose two different evaluation methods for the CGP: to minimize the number of AIG nodes or optimize the circuit accuracy. We obtain at least 22.6% superior results when considering the ratio between accuracy and size for the benchmarks used, compared with the teams from the IWLS 2020 contest that obtained the best accuracy and size results. It is noteworthy that any logic synthesis approach based on AIGs can easily incorporate the proposed flow. The results obtained show that their usage may achieve improved logic circuits.","PeriodicalId":270661,"journal":{"name":"2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116924301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

0.5 V 19 nW Smart Temperature Sensor for Ultra-Low-Power CMOS Applications 用于超低功耗CMOS应用的0.5 V 19 nW智能温度传感器

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529980

Daniel C. Lott, Dalton Martini Colombo

引用次数: 2

High-Throughput Sharp Interpolation Filter Hardware Architecture for the AV1 Video Codec AV1视频编解码器的高吞吐量锐插值滤波器硬件架构

2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2021-08-23 DOI: 10.1109/SBCCI53441.2021.9529993

Daiane Freitas, C. Diniz, M. Grellert, G. Corrêa

引用次数: 5