Vassilis Alimisis, Marios Gourdouparis, Christos Dimas, P. Sotiriadis
{"title":"一个0.6 V, 3.3 nW,可调高斯电路可调谐核函数","authors":"Vassilis Alimisis, Marios Gourdouparis, Christos Dimas, P. Sotiriadis","doi":"10.1109/SBCCI53441.2021.9529988","DOIUrl":null,"url":null,"abstract":"This work introduces a compact, ultra-low power (3.3nW) Gaussian circuit architecture for Kernel function emulation. It has independent and electronically adjustable mean value, amplitude and deviation, operating with 0.6V power supply. It consists of a current correlator and a bulk-controlled differential block, with all transistors operating in sub-threshold. Proper operation, accuracy and sensitivity are confirmed via post-layout simulation results and theoretical analysis. It was implemented in TSMC 90nm CMOS process and simulated using the Cadence IC Suite.","PeriodicalId":270661,"journal":{"name":"2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 0.6 V, 3.3 nW, Adjustable Gaussian Circuit for Tunable Kernel Functions\",\"authors\":\"Vassilis Alimisis, Marios Gourdouparis, Christos Dimas, P. Sotiriadis\",\"doi\":\"10.1109/SBCCI53441.2021.9529988\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work introduces a compact, ultra-low power (3.3nW) Gaussian circuit architecture for Kernel function emulation. It has independent and electronically adjustable mean value, amplitude and deviation, operating with 0.6V power supply. It consists of a current correlator and a bulk-controlled differential block, with all transistors operating in sub-threshold. Proper operation, accuracy and sensitivity are confirmed via post-layout simulation results and theoretical analysis. It was implemented in TSMC 90nm CMOS process and simulated using the Cadence IC Suite.\",\"PeriodicalId\":270661,\"journal\":{\"name\":\"2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SBCCI53441.2021.9529988\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBCCI53441.2021.9529988","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
摘要
本文介绍了一种用于核函数仿真的紧凑、超低功耗(3.3nW)高斯电路架构。具有独立的、电子可调的平均值、幅值和偏差,工作电源为0.6V。它由一个电流相关器和一个体控差分块组成,所有晶体管都工作在亚阈值下。通过布局后仿真结果和理论分析,验证了该方法的正确性、精度和灵敏度。采用台积电90nm CMOS工艺实现,并采用Cadence IC Suite进行仿真。
A 0.6 V, 3.3 nW, Adjustable Gaussian Circuit for Tunable Kernel Functions
This work introduces a compact, ultra-low power (3.3nW) Gaussian circuit architecture for Kernel function emulation. It has independent and electronically adjustable mean value, amplitude and deviation, operating with 0.6V power supply. It consists of a current correlator and a bulk-controlled differential block, with all transistors operating in sub-threshold. Proper operation, accuracy and sensitivity are confirmed via post-layout simulation results and theoretical analysis. It was implemented in TSMC 90nm CMOS process and simulated using the Cadence IC Suite.