Configurable Approximate Hardware Accelerator to Compute SATD and SAD Metrics for Low Power All-Intra High Efficiency Video Coding

Abstract

Connecting billions of network cameras to the cloud is a challenge that heavily taxes the network bandwidth for video transmissions. High Efficiency Video Coding (HEVC) standard offers a good option from the bit-rate reduction and video quality perspectives, but it is more computational complex than previous standards. This paper uses HEVC All-Intra configuration in this context, thus simplifying video encoding by avoiding interframe prediction, and by using VLSI hardware acceleration and approximate computing. Sum of Absolute Transformed Differences (SATD) is a distortion metric used in intra-mode decision fast algorithm and consumes a significant part of intra-frame encoding execution time in software. This work proposes a configurable-approximate hardware accelerator supporting 8 × 8 SATD, the simpler Sum of Absolute Differences (SAD) metric, and two approximate SATD versions by excluding columns of arithmetic operators of the 8 × 8 Hadamard Transform. When operating in three-columns exclusion, five-columns exclusion, and SAD configurations, the total VLSI power dissipation is reduced by 19.87%, 32.33% and 39.16% respectively, when compared to precise SATD computation.