High-Throughput and Low-Power Architectures for the AV1 Arithmetic Encoder

Abstract

With the emerging interest in video-on-demand systems, streaming service providers shall acclimate their systems to decrease the global Internet infrastructure impact caused by videos. Video coding standards are presented as a powerful but complex solution for this problem. Hence, to tackle these tools' complexity and allow a better codification flow, hardware designs arise as options for decreasing the bottleneck of video-on-demand systems. This paper presents a hardware architecture, named AE-AV1, that aims to entirely execute the arithmetic encoding process of the AV1 codec while achieving enough throughput rate for an ultra-high performance (i.e., 8K@120fps real-time codification). Moreover, this document also propounds the LP-AE-AV1 architecture, which represents a low-power version of the AE-AV1.