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International Symposium on VLSI Design and Test最新文献

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An Efficient Test and Fault Tolerance Technique for Paper-Based DMFB 基于纸张的DMFB的有效测试和容错技术
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_7
Chandan Das, Sarit Chakraborty, Susanta Chakraborty
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引用次数: 0
A 1.25-20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s SerDes Application 一种用于40gb /s SerDes的1.25-20 GHz宽调谐范围频率合成方法
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_3
Javed S. Gaggatur, A. Chaturvedi
{"title":"A 1.25-20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s SerDes Application","authors":"Javed S. Gaggatur, A. Chaturvedi","doi":"10.1007/978-981-32-9767-8_3","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_3","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126612291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods 识别有效的指导提示，以更好地通过形式化方法进行设计调试
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_35
Vineesh V S, Binod Kumar, Jay Adhaduk
{"title":"Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods","authors":"Vineesh V S, Binod Kumar, Jay Adhaduk","doi":"10.1007/978-981-32-9767-8_35","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_35","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127426898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Latency and Throughput Efficient Successive Cancellation Decoding of Polar Codes 一种延迟和吞吐量高效的极性码连续对消译码
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_61
S. Manasa, G. L. Narayanan
{"title":"A Latency and Throughput Efficient Successive Cancellation Decoding of Polar Codes","authors":"S. Manasa, G. L. Narayanan","doi":"10.1007/978-981-32-9767-8_61","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_61","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127504734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications 基于SiGe圆柱隧道晶体管的低功耗紧凑脉冲神经网络系统
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_54
A. Beohar, Gopal R. Raut, Gunjan Rajput, Abhinav Vishwakarma, A. P. Shah, B. Reniwal, S. Vishvakarma
{"title":"Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications","authors":"A. Beohar, Gopal R. Raut, Gunjan Rajput, Abhinav Vishwakarma, A. P. Shah, B. Reniwal, S. Vishvakarma","doi":"10.1007/978-981-32-9767-8_54","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_54","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133108294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications 一种基于CMOS/MTJ的新型非易失性SRAM单元，具有常关应用的异步写终止
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_46
Kanika Monga, N. Chaturvedi
{"title":"A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications","authors":"Kanika Monga, N. Chaturvedi","doi":"10.1007/978-981-32-9767-8_46","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_46","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128995425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models 基于回归模型的16nm VLSI数字电路统计变异感知漏电和总功率估计
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_47
Deepthi Amuru, Andleeb Zahra, Zia Abbas
{"title":"Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models","authors":"Deepthi Amuru, Andleeb Zahra, Zia Abbas","doi":"10.1007/978-981-32-9767-8_47","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_47","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130899415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap 栅极-漏极下覆的III-V型横向隧道场效应管的仿真研究
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_59
Venkata Appa Rao Yempada, S. Jandhyala
{"title":"Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap","authors":"Venkata Appa Rao Yempada, S. Jandhyala","doi":"10.1007/978-981-32-9767-8_59","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_59","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133505150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
2L-2D Routing for Buffered Mesh Network-on-Chip 缓冲网状片上网络的2L-2D路由
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_27
Rose George Kunthara, K. Neethu, R. K. James, Simi Zerine Sleeba, Tripti S. Warrier, John Jose
{"title":"2L-2D Routing for Buffered Mesh Network-on-Chip","authors":"Rose George Kunthara, K. Neethu, R. K. James, Simi Zerine Sleeba, Tripti S. Warrier, John Jose","doi":"10.1007/978-981-32-9767-8_27","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_27","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122623056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Unified Methodology for Hardware Obfuscation and IP Watermarking 硬件混淆和IP水印的统一方法
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_23
Saurabh Gangurde, Binod Kumar
{"title":"A Unified Methodology for Hardware Obfuscation and IP Watermarking","authors":"Saurabh Gangurde, Binod Kumar","doi":"10.1007/978-981-32-9767-8_23","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_23","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124716887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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