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International Symposium on VLSI Design and Test最新文献

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A Complete Hardware Advent on IEEE 802.15.4 Based Mac Layer and a Comparison with Open-ZB 基于IEEE 802.15.4的Mac层硬件实现及与Open-ZB的比较
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_56
A. Rajesh, Sanket V. Kadam, R. Patrikar
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引用次数: 1
Efficient Hardware-Software Codesigns of AES Encryptor and RS-BCH Encoder AES加密器和RS-BCH编码器的高效软硬件协同设计
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_1
M. Basiri, S. Shukla
{"title":"Efficient Hardware-Software Codesigns of AES Encryptor and RS-BCH Encoder","authors":"M. Basiri, S. Shukla","doi":"10.1007/978-981-13-5950-7_1","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_1","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116667076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips 基于树状网格的片上网络容错路由算法
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_38
Monil Shah, Mohit Upadhyay, P. V. Bhanu, J. Soumya, Linga Reddy Cenkeramaddi
{"title":"A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips","authors":"Monil Shah, Mohit Upadhyay, P. V. Bhanu, J. Soumya, Linga Reddy Cenkeramaddi","doi":"10.1007/978-981-13-5950-7_38","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_38","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116379035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Comparative Exploration About Approximate Full Adders for Error Tolerant Applications 容错应用中近似全加法器的比较探讨
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_6
M. Priyadharshni, S. Kumaravel
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引用次数: 2
Design and Fabrication of Versatile Low Power Wireless Sensor Nodes for IoT Applications 面向物联网应用的多用途低功耗无线传感器节点的设计与制造
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_58
Saket Thool, R. Deshmukh, R. Patrikar
{"title":"Design and Fabrication of Versatile Low Power Wireless Sensor Nodes for IoT Applications","authors":"Saket Thool, R. Deshmukh, R. Patrikar","doi":"10.1007/978-981-13-5950-7_58","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_58","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133691029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Approach to Detect Hardware Malware Using Hamming Weight Model and One Class Support Vector Machine 基于Hamming权重模型和一类支持向量机的硬件恶意软件检测方法
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_14
P. Saravanan, B. Mehtre
{"title":"A Novel Approach to Detect Hardware Malware Using Hamming Weight Model and One Class Support Vector Machine","authors":"P. Saravanan, B. Mehtre","doi":"10.1007/978-981-13-5950-7_14","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_14","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123141472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fabrication and LBM-Modeling of Directional Fluid Transport on Low-Cost Electro-Osmotic Flow Device 低成本电渗透定向流体输送装置的制造与lbm建模
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_53
T. Pravinraj, R. Patrikar
{"title":"Fabrication and LBM-Modeling of Directional Fluid Transport on Low-Cost Electro-Osmotic Flow Device","authors":"T. Pravinraj, R. Patrikar","doi":"10.1007/978-981-13-5950-7_53","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_53","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"83 19","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120824837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks 增强逻辑锁定安全硬件IP防止猜键攻击
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_16
S. Rajendran, M. N. Devi
{"title":"Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks","authors":"S. Rajendran, M. N. Devi","doi":"10.1007/978-981-13-5950-7_16","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_16","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114814092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Methodology to Design Online Testable Reversible Circuits 一种在线可测试可逆电路的设计方法
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_28
Mrinal Goswami, Govind Raj, A. Narzary, B. Sen
{"title":"A Methodology to Design Online Testable Reversible Circuits","authors":"Mrinal Goswami, Govind Raj, A. Narzary, B. Sen","doi":"10.1007/978-981-13-5950-7_28","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_28","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129071044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High Level Synthesis and Implementation of Cryptographic Algorithm in AHIR Platform AHIR平台上密码算法的高级综合与实现
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_2
Abhimanniu Raveendran, S. B. Dhok, R. Patrikar
{"title":"High Level Synthesis and Implementation of Cryptographic Algorithm in AHIR Platform","authors":"Abhimanniu Raveendran, S. B. Dhok, R. Patrikar","doi":"10.1007/978-981-13-5950-7_2","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_2","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121776185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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