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A Novel Countermeasure Against Differential Scan Attack in AES Algorithm AES算法中对抗差分扫描攻击的新方法
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_26
J. Popat, U. Mehta
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引用次数: 2
A Heuristic Qubit Placement Strategy for Nearest Neighbor Realization in 2D Architecture 二维结构中最近邻实现的启发式量子位放置策略
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_49
Anirban Bhattacharjee, Chandan Bandyopadhyay, L. Biswal, H. Rahaman
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引用次数: 4
Continuous Flow Microfluidic Channel Design for Blood Plasma Separation 用于血浆分离的连续流微流控通道设计
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_23
Jagriti Srivastava, R. Patrikar
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引用次数: 0
An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC) 一种基于片上网络(NoC)的节能核心映射算法
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_52
B. N. K. Reddy, Sireesha
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引用次数: 12
Deadlock Detection in Digital Microfluidics Biochip Droplet Routing 数字微流体生物芯片液滴路径中的死锁检测
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_21
Jyotiranjan Swain, Sumanta Pyne
{"title":"Deadlock Detection in Digital Microfluidics Biochip Droplet Routing","authors":"Jyotiranjan Swain, Sumanta Pyne","doi":"10.1007/978-981-13-5950-7_21","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_21","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133438477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Robust SRAM Cell Development for Single-Event Multiple Effects 单事件多重效应的稳健SRAM单元开发
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_29
CH NagaRaghuram, D. Reddy, P. Kumar, G. Kaushal
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引用次数: 3
Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power 减小待机漏功率的全加法器块晶体管最佳尺寸
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_8
Prateek Gupta, Shubham Kumar, Zia Abbas
{"title":"Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power","authors":"Prateek Gupta, Shubham Kumar, Zia Abbas","doi":"10.1007/978-981-13-5950-7_8","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_8","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126199815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Novel Design Approach to Implement Multi-port Register Files Using Pulsed-Latches 一种利用脉冲锁存器实现多端口寄存器文件的新设计方法
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_44
T. Manivannan, M. Srinivasan
{"title":"A Novel Design Approach to Implement Multi-port Register Files Using Pulsed-Latches","authors":"T. Manivannan, M. Srinivasan","doi":"10.1007/978-981-13-5950-7_44","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_44","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121308863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 31 ppm/° C Pure CMOS Bandgap Reference by Exploiting Beta-Multiplier 利用beta倍增器的31 ppm/°C纯CMOS带隙基准
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_9
R. Nagulapalli, K. Hayatleh, S. Barker, Saddam Zourob, N. Yassine, B. N. K. Reddy
{"title":"A 31 ppm/° C Pure CMOS Bandgap Reference by Exploiting Beta-Multiplier","authors":"R. Nagulapalli, K. Hayatleh, S. Barker, Saddam Zourob, N. Yassine, B. N. K. Reddy","doi":"10.1007/978-981-13-5950-7_9","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_9","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117160052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations 基于FPGA和ASIC实现的当前分组密码的VLSI架构
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_18
J. Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Sajid Khan, S. Vishvakarma, A. Karmakar, Raj Singh
{"title":"A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations","authors":"J. Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Sajid Khan, S. Vishvakarma, A. Karmakar, Raj Singh","doi":"10.1007/978-981-13-5950-7_18","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_18","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123090040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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