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International Symposium on VLSI Design and Test最新文献

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A Space Efficient Greedy Droplet Routing for Digital Microfluidics Biochip 数字微流控生物芯片的空间高效贪心液滴路径
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_9
Jyotiranjan Swain, Rajesh Kolluri, Sumanta Pyne
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引用次数: 4
Utilizing NBTI for Operation Detection of Integrated Circuits 利用NBTI进行集成电路的运行检测
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_17
A. P. Shah, Amirhossein Moshrefi, M. Waltl
{"title":"Utilizing NBTI for Operation Detection of Integrated Circuits","authors":"A. P. Shah, Amirhossein Moshrefi, M. Waltl","doi":"10.1007/978-981-32-9767-8_17","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_17","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125692175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture 基于多应用的可重构网格拓扑容错片上网络设计
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_37
P. V. Bhanu, P. Kulkarni, Sai Pranavi Avadhanam, J. Soumya, Linga Reddy Cenkeramaddi
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引用次数: 2
Delay Efficient All Optical Carry Lookahead Adder 延迟高效全光进位前瞻加法器
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_21
Sayantani Roy, Arighna Deb, D. K. Das
{"title":"Delay Efficient All Optical Carry Lookahead Adder","authors":"Sayantani Roy, Arighna Deb, D. K. Das","doi":"10.1007/978-981-32-9767-8_21","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_21","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131267332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
GaAs-SiGe Based Novel Device Structure of Doping Less Tunnel FET 基于GaAs-SiGe的新型无掺杂隧道场效应管器件结构
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_57
Shivendra Yadav, Chithraja Rajan, D. Sharma, Sanjay Balotiya
{"title":"GaAs-SiGe Based Novel Device Structure of Doping Less Tunnel FET","authors":"Shivendra Yadav, Chithraja Rajan, D. Sharma, Sanjay Balotiya","doi":"10.1007/978-981-32-9767-8_57","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_57","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"20-28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133814504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A CMOS Low Noise Amplifier with Improved Gain 一种增益改进的CMOS低噪声放大器
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_19
Sunanda Ambulker, J. Mishra, Sangeeta Nakhate
{"title":"A CMOS Low Noise Amplifier with Improved Gain","authors":"Sunanda Ambulker, J. Mishra, Sangeeta Nakhate","doi":"10.1007/978-981-32-9767-8_19","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_19","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115725175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Brain Inspired One Shot Learning Method for HD Computing 大脑启发的高清计算一次性学习方法
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_25
D. R. Nair, A. Purushothaman
{"title":"Brain Inspired One Shot Learning Method for HD Computing","authors":"D. R. Nair, A. Purushothaman","doi":"10.1007/978-981-32-9767-8_25","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_25","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114328720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model 基于BSIM-BULK模型的漏极扩展MOS晶体管紧凑建模
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_55
S. S. Parihar, R. Gurjar
{"title":"Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model","authors":"S. S. Parihar, R. Gurjar","doi":"10.1007/978-981-32-9767-8_55","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_55","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114525644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved Performance 一种新颖的基于20nm FinFET的10T SRAM单元设计，以提高性能
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_43
Anushka Singh, Yash Sharma, A. Sharma, A. Pandey
{"title":"A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved Performance","authors":"Anushka Singh, Yash Sharma, A. Sharma, A. Pandey","doi":"10.1007/978-981-32-9767-8_43","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_43","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117048625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 2.4 GHz High Efficiency Capacitive Cross Coupled Common Gate Class-E Differential Power Amplifier 2.4 GHz高效电容交叉耦合共门e类差分功率放大器
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_2
A. Sunitha, Bhaskar Manickam
{"title":"A 2.4 GHz High Efficiency Capacitive Cross Coupled Common Gate Class-E Differential Power Amplifier","authors":"A. Sunitha, Bhaskar Manickam","doi":"10.1007/978-981-32-9767-8_2","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_2","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126416573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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