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International Symposium on VLSI Design and Test最新文献

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Design of Current Mode Sigmoid Function and Hyperbolic Tangent Function 电流模Sigmoid函数和双曲正切函数的设计
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_5
D. Datta, Sweta Agarwal, Vikash Kumar, M. Raj, B. Ray, A. Banerjee
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引用次数: 5
ASIC Based LVDT Signal Conditioner for High-Accuracy Measurements 基于ASIC的高精度测量LVDT信号调节器
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_33
K. P. Raghunath, K. Sagar, T. Gokulan, Kundan Kumar, C. S. Thakur
{"title":"ASIC Based LVDT Signal Conditioner for High-Accuracy Measurements","authors":"K. P. Raghunath, K. Sagar, T. Gokulan, Kundan Kumar, C. S. Thakur","doi":"10.1007/978-981-32-9767-8_33","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_33","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131567235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-Voltage Dual-Gate Organic Thin Film Transistors with Distinctly Placed Source and Drain 具有明显源极和漏极位置的低压双栅有机薄膜晶体管
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_60
Shagun Pal, B. Kumar
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引用次数: 0
Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit 浮点乘加电路的异步硬件设计
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_22
M. Basiri
{"title":"Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit","authors":"M. Basiri","doi":"10.1007/978-981-32-9767-8_22","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_22","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117315682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Approach for Detection of Node Displacement Fault (NDF) in Reversible Circuit 可逆电路中节点位移故障(NDF)的检测方法
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_50
Bappaditya Mondal, Anirban Bhattacharjee, Subham Saha, Shalini Parekh, Chandan Bandyopadhyay, H. Rahaman
{"title":"An Approach for Detection of Node Displacement Fault (NDF) in Reversible Circuit","authors":"Bappaditya Mondal, Anirban Bhattacharjee, Subham Saha, Shalini Parekh, Chandan Bandyopadhyay, H. Rahaman","doi":"10.1007/978-981-32-9767-8_50","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_50","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127889259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Threshold Implementation of a Low-Cost CLEFIA-128 Cipher for Power Analysis Attack Resistance 低成本CLEFIA-128密码抗功率分析攻击的阈值实现
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_24
S. Rekha, P. Saravanan
{"title":"Threshold Implementation of a Low-Cost CLEFIA-128 Cipher for Power Analysis Attack Resistance","authors":"S. Rekha, P. Saravanan","doi":"10.1007/978-981-32-9767-8_24","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_24","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127947498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On-Chip Threshold Compensated Voltage Doubler for RF Energy Harvesting 用于射频能量收集的片上阈值补偿倍压器
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_16
A. Mohan, Saroj Mondal, S. Dan
{"title":"On-Chip Threshold Compensated Voltage Doubler for RF Energy Harvesting","authors":"A. Mohan, Saroj Mondal, S. Dan","doi":"10.1007/978-981-32-9767-8_16","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_16","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130352575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA Multi-core Architectures 异构isa多核架构的性能建模与动态调度
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_58
N. Boran, D. K. Yadav, Rishabh R. Iyer
{"title":"Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA Multi-core Architectures","authors":"N. Boran, D. K. Yadav, Rishabh R. Iyer","doi":"10.1007/978-981-32-9767-8_58","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_58","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132294850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An Efficient Wireless Charging Technique Using Inductive and Resonant Circuits 一种利用感应和谐振电路的高效无线充电技术
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_14
Purvi Agrawal, Ruchi Dhamnani, Ananya Garg, S. Tripathi, M. Majumder
{"title":"An Efficient Wireless Charging Technique Using Inductive and Resonant Circuits","authors":"Purvi Agrawal, Ruchi Dhamnani, Ananya Garg, S. Tripathi, M. Majumder","doi":"10.1007/978-981-32-9767-8_14","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_14","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128736173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigating the Role of Parasitic Resistance in a Class of Nanoscale Interconnects 研究一类纳米级互连中寄生电阻的作用
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_31
Shahid Yousuf, A. Bhardwaj, Rohit Sharma
{"title":"Investigating the Role of Parasitic Resistance in a Class of Nanoscale Interconnects","authors":"Shahid Yousuf, A. Bhardwaj, Rohit Sharma","doi":"10.1007/978-981-32-9767-8_31","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_31","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116297746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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