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A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations

International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI:10.1007/978-981-13-5950-7_18
J. Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Sajid Khan, S. Vishvakarma, A. Karmakar, Raj Singh
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引用次数: 2
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基于FPGA和ASIC实现的当前分组密码的VLSI架构
本文章由计算机程序翻译，如有差异，请以英文原文为准。
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International Symposium on VLSI Design and Test
International Symposium on VLSI Design and Test
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