发布求助
文献互助 智能选刊 最新文献

International Symposium on VLSI Design and Test最新文献

筛选
英文 中文
Heuristic Driven Genetic Algorithm for Priority Assignment of Real-Time Communications in NoC NoC实时通信优先级分配的启发式驱动遗传算法
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_37
Ajay Khare, Chinmay Patil, Manikanta Nallamalli, S. Chattopadhyay
{"title":"Heuristic Driven Genetic Algorithm for Priority Assignment of Real-Time Communications in NoC","authors":"Ajay Khare, Chinmay Patil, Manikanta Nallamalli, S. Chattopadhyay","doi":"10.1007/978-981-13-5950-7_37","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_37","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123511328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of CMOS Based Biosensor for Implantable Medical Devices 基于CMOS的植入式医疗设备生物传感器设计
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_57
G. Gifta, D. Rani, Nifasath Farhana, R. Archana
{"title":"Design of CMOS Based Biosensor for Implantable Medical Devices","authors":"G. Gifta, D. Rani, Nifasath Farhana, R. Archana","doi":"10.1007/978-981-13-5950-7_57","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_57","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122129021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Novel RF MEMS Capacitive Switch for Lower Actuation Voltage 低驱动电压的新型射频MEMS电容开关
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_25
S. B. Dhule, Vasu Pulijala
{"title":"Novel RF MEMS Capacitive Switch for Lower Actuation Voltage","authors":"S. B. Dhule, Vasu Pulijala","doi":"10.1007/978-981-13-5950-7_25","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_25","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126778285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel March C2RR Algorithm for Nanoelectronic Resistive Random Access Memory (RRAM) Testing 纳米电子电阻性随机存取存储器(RRAM)测试的新颖March C2RR算法
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_48
H. Sribhuvaneshwari, K. Suthendran
{"title":"A Novel March C2RR Algorithm for Nanoelectronic Resistive Random Access Memory (RRAM) Testing","authors":"H. Sribhuvaneshwari, K. Suthendran","doi":"10.1007/978-981-13-5950-7_48","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_48","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126601391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Efficient and Failure Aware ECC for STT-MRAM Cache Memory 高效和故障感知的STT-MRAM高速缓存ECC
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_43
Keerthi Sagar Kokkiligadda, Yogendra Gupta, Lava Bhargava
{"title":"Efficient and Failure Aware ECC for STT-MRAM Cache Memory","authors":"Keerthi Sagar Kokkiligadda, Yogendra Gupta, Lava Bhargava","doi":"10.1007/978-981-13-5950-7_43","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_43","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129162199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of High Speed 5: 2 and 7: 2 Compressor Using Nanomagnetic Logic 采用纳米磁逻辑设计高速5:2和7:2压缩机
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_5
Shantanu Agarwal, G. Harish, S. Balamurugan, R. Marimuthu
{"title":"Design of High Speed 5: 2 and 7: 2 Compressor Using Nanomagnetic Logic","authors":"Shantanu Agarwal, G. Harish, S. Balamurugan, R. Marimuthu","doi":"10.1007/978-981-13-5950-7_5","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_5","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127375971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Layout Design of X-Band Low Noise Amplifier for Radar Applications 雷达用x波段低噪声放大器布局设计
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_13
I. Stefigraf, S. Rajaram
{"title":"Layout Design of X-Band Low Noise Amplifier for Radar Applications","authors":"I. Stefigraf, S. Rajaram","doi":"10.1007/978-981-13-5950-7_13","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_13","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117249505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SARP: Self Aware Runtime Protection Against Integrity Attacks of Hardware Trojans SARP:针对硬件木马完整性攻击的自我意识运行时保护
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_17
Krishnendu Guha, Debasri Saha, A. Chakrabarti
{"title":"SARP: Self Aware Runtime Protection Against Integrity Attacks of Hardware Trojans","authors":"Krishnendu Guha, Debasri Saha, A. Chakrabarti","doi":"10.1007/978-981-13-5950-7_17","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_17","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124446532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip 片上网状网络容错路由技术的实现
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_42
P. AkshayB., M. GaneshK., R. ThippeswamyD., Vishnu S. Bhat, A. Vijayakumar, R. AnandaY., John Jose
{"title":"Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip","authors":"P. AkshayB., M. GaneshK., R. ThippeswamyD., Vishnu S. Bhat, A. Vijayakumar, R. AnandaY., John Jose","doi":"10.1007/978-981-13-5950-7_42","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_42","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121580662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Performance Enhancement of NoCs Using Single Cycle Deflection Routers and Adaptive Priority Schemes 利用单周期偏转路由器和自适应优先级方案增强noc性能
International Symposium on VLSI Design and Test Pub Date : 2018-06-28 DOI: 10.1007/978-981-13-5950-7_39
K. S. Midhula, Sarath Babu, John Jose, Sangeetha Jose
{"title":"Performance Enhancement of NoCs Using Single Cycle Deflection Routers and Adaptive Priority Schemes","authors":"K. S. Midhula, Sarath Babu, John Jose, Sangeetha Jose","doi":"10.1007/978-981-13-5950-7_39","DOIUrl":"https://doi.org/10.1007/978-981-13-5950-7_39","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123222842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信