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Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap

International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI:10.1007/978-981-32-9767-8_59
Venkata Appa Rao Yempada, S. Jandhyala
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栅极-漏极下覆的III-V型横向隧道场效应管的仿真研究
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International Symposium on VLSI Design and Test
International Symposium on VLSI Design and Test
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