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International Symposium on VLSI Design and Test最新文献

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Radiation Hardened by Design Sense Amplifier 设计感测放大器抗辐射
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_20
Avinash Verma, G. Kaushal
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引用次数: 0
Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard HEVC标准的质量驱动能量感知近似核心变换体系结构
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_34
Neelam Arya, A. Rajput, M. Pattanaik, G. K. Sharma
{"title":"Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard","authors":"Neelam Arya, A. Rajput, M. Pattanaik, G. K. Sharma","doi":"10.1007/978-981-32-9767-8_34","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_34","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126784902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Approximate Computing Based Adder Design for DWT Application 基于近似计算的DWT加法器设计
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_13
Moumita Acharya, Samik Basu, Biranchi Narayan Behera, A. Chakrabarti
{"title":"Approximate Computing Based Adder Design for DWT Application","authors":"Moumita Acharya, Samik Basu, Biranchi Narayan Behera, A. Chakrabarti","doi":"10.1007/978-981-32-9767-8_13","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_13","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129320132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a Power Efficient Pulse Latch Circuit as a Solution for Master Slave Flip-Flop 一种高效功率脉冲锁存电路的设计，作为主从触发器的解决方案
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_44
M. Sulthan, Shubhajit Roy Chowdury, R. Garg, Alok Tripathi
{"title":"Design of a Power Efficient Pulse Latch Circuit as a Solution for Master Slave Flip-Flop","authors":"M. Sulthan, Shubhajit Roy Chowdury, R. Garg, Alok Tripathi","doi":"10.1007/978-981-32-9767-8_44","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_44","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129333658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Ultra Low Power AES Architecture for IoT 物联网超低功耗AES架构
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_29
Sajid Khan, N. Gupta, Gopal R. Raut, Gunjan Rajput, J. Pandey, S. Vishvakarma
{"title":"An Ultra Low Power AES Architecture for IoT","authors":"Sajid Khan, N. Gupta, Gopal R. Raut, Gunjan Rajput, J. Pandey, S. Vishvakarma","doi":"10.1007/978-981-32-9767-8_29","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_29","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114188703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS 用于1.2 V, 65nm CMOS多相时钟产生的宽线性，功率高效，电荷控制延迟元件
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_18
Raviteja Kammari, V. Pasupureddi
{"title":"A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS","authors":"Raviteja Kammari, V. Pasupureddi","doi":"10.1007/978-981-32-9767-8_18","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_18","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127702785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel Approach for Improved Signal Integrity and Power Dissipation Using MLGNR Interconnects 利用MLGNR互连提高信号完整性和功耗的新方法
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_51
Vijay Rao Kumbhare, P. Paltani, M. Majumder
{"title":"Novel Approach for Improved Signal Integrity and Power Dissipation Using MLGNR Interconnects","authors":"Vijay Rao Kumbhare, P. Paltani, M. Majumder","doi":"10.1007/978-981-32-9767-8_51","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_51","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123116215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network 人工神经网络硬件实现的高效低精度CORDIC算法
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_28
Gopal R. Raut, Vishal Bhartiy, Gunjan Rajput, Sajid Khan, A. Beohar, S. Vishvakarma
{"title":"Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network","authors":"Gopal R. Raut, Vishal Bhartiy, Gunjan Rajput, Sajid Khan, A. Beohar, S. Vishvakarma","doi":"10.1007/978-981-32-9767-8_28","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_28","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123138916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Automations and Methodologies for Efficient and Quality Conscious Analog Layout Implementation 高效和质量意识模拟布局实现的自动化和方法
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_1
Varun Kumar Dwivedi, Madhvi Sharma, Chandaka Venu
{"title":"Automations and Methodologies for Efficient and Quality Conscious Analog Layout Implementation","authors":"Varun Kumar Dwivedi, Madhvi Sharma, Chandaka Venu","doi":"10.1007/978-981-32-9767-8_1","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_1","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116889127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Gate-Level On-Chip Crosstalk Noise Reduction Circuit for Deep Sub-micron Technology 一种新型的深亚微米技术门级片上串扰降噪电路
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_15
Swatilekha Majumdar
{"title":"A Novel Gate-Level On-Chip Crosstalk Noise Reduction Circuit for Deep Sub-micron Technology","authors":"Swatilekha Majumdar","doi":"10.1007/978-981-32-9767-8_15","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_15","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132794048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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