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A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS

International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI:10.1007/978-981-32-9767-8_18
Raviteja Kammari, V. Pasupureddi
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用于1.2 V, 65nm CMOS多相时钟产生的宽线性，功率高效，电荷控制延迟元件
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International Symposium on VLSI Design and Test
International Symposium on VLSI Design and Test
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