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International Symposium on VLSI Design and Test最新文献

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Comparative Analysis of Logic Gates Based on Spin Transfer Torque (STT) and Differential Spin Hall Effect (DSHE) Switching Mechanisms 基于自旋传递扭矩(STT)和微分自旋霍尔效应(DSHE)开关机制的逻辑门的比较分析
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_36
Piyush Tankwal, V. Nehra, B. Kaushik
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引用次数: 2
Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell 低漏，高稳定，鲁棒超低功耗8T SRAM电池
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_53
N. Gupta, Tanisha Gupta, Sajid Khan, Abhinav Vishwakarma, S. Vishvakarma
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引用次数: 2
Intelligent Traffic Light Controller: A Solution for Smart City Traffic Problem 智能交通灯控制器:智慧城市交通问题的解决方案
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_63
Almas Sabir, Anushree Jain, Yashwini Nathwani, V. Neema
{"title":"Intelligent Traffic Light Controller: A Solution for Smart City Traffic Problem","authors":"Almas Sabir, Anushree Jain, Yashwini Nathwani, V. Neema","doi":"10.1007/978-981-32-9767-8_63","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_63","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"265 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123402398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Realistic Configurable Level Triggered Flip-Flop in Quantum-Dot Cellular Automata 量子点元胞自动机中一种现实的可配置电平触发触发器
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_38
Mrinal Goswami, M. Choudhury, B. Sen
{"title":"A Realistic Configurable Level Triggered Flip-Flop in Quantum-Dot Cellular Automata","authors":"Mrinal Goswami, M. Choudhury, B. Sen","doi":"10.1007/978-981-32-9767-8_38","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_38","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123704954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Efficient Closely-Coupled Integration of AES Coprocessor with LEON3 Processor AES协处理器与LEON3处理器的高效紧密耦合集成
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_30
R. Bansal, A. Karmakar
{"title":"Efficient Closely-Coupled Integration of AES Coprocessor with LEON3 Processor","authors":"R. Bansal, A. Karmakar","doi":"10.1007/978-981-32-9767-8_30","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_30","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121163529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM Cell 一个健壮的低功率写辅助数据依赖电源供应的12T SRAM单元
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_52
N. Gupta, J. Prasad, Rana Sagar Kumar, Gunjan Rajput, S. Vishvakarma
{"title":"A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM Cell","authors":"N. Gupta, J. Prasad, Rana Sagar Kumar, Gunjan Rajput, S. Vishvakarma","doi":"10.1007/978-981-32-9767-8_52","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_52","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124823327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU 基于RISC-V指令集的高级语言建模FPU功能仿真验证
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_41
Aneesh Raveendran, Vinay B. Y. Kumar, Vivian Desalphine, D. Selvakumar
{"title":"Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU","authors":"Aneesh Raveendran, Vinay B. Y. Kumar, Vivian Desalphine, D. Selvakumar","doi":"10.1007/978-981-32-9767-8_41","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_41","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126417808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dual-Edge Triggered Lightweight Implementation of AES for IoT Security 用于物联网安全的双边缘触发轻量级AES实现
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_26
Sajid Khan, N. Gupta, Abhinav Vishwakarma, S. Chouhan, J. Pandey, S. Vishvakarma
{"title":"Dual-Edge Triggered Lightweight Implementation of AES for IoT Security","authors":"Sajid Khan, N. Gupta, Abhinav Vishwakarma, S. Chouhan, J. Pandey, S. Vishvakarma","doi":"10.1007/978-981-32-9767-8_26","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_26","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121836927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
User Guided Register Manipulation in Digital Circuits 数字电路中用户引导的寄存器操作
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_39
P. Panigrahi, R. Jha, C. Karfa
{"title":"User Guided Register Manipulation in Digital Circuits","authors":"P. Panigrahi, R. Jha, C. Karfa","doi":"10.1007/978-981-32-9767-8_39","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_39","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121817344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor RISC-V半精度浮点指令集扩展和协处理器
International Symposium on VLSI Design and Test Pub Date : 2019-07-04 DOI: 10.1007/978-981-32-9767-8_40
Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, A. Selvakumar
{"title":"RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor","authors":"Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, A. Selvakumar","doi":"10.1007/978-981-32-9767-8_40","DOIUrl":"https://doi.org/10.1007/978-981-32-9767-8_40","url":null,"abstract":"","PeriodicalId":270429,"journal":{"name":"International Symposium on VLSI Design and Test","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114460170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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