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IEEE Custom Integrated Circuits Conference 2006最新文献

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A Wideband ΔΣ Digital-RF Modulator With Self-Tuned RF Bandpass Reconstruction Filter 带自调谐射频带通重构滤波器的宽带ΔΣ数字射频调制器
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320848
A. Jerng, C. Sodini
{"title":"A Wideband ΔΣ Digital-RF Modulator With Self-Tuned RF Bandpass Reconstruction Filter","authors":"A. Jerng, C. Sodini","doi":"10.1109/CICC.2006.320848","DOIUrl":"https://doi.org/10.1109/CICC.2006.320848","url":null,"abstract":"A low power, wideband transmitter architecture utilizing ΔΣ direct digital modulation of an RF carrier is presented. Spurious signals associated with direct digital-RF conversion are eliminated through integration of a self-tuned passive LC bandpass filter. The digital-RF modulator is intended for OFDM systems and can provide data rates greater than 1 Gb/s using a bandwidth of 200 MHz centered at 5.25 GHz. Measured results show that the largest modulator spur is -44 dBc. The transmitter, including LO quadrature generator, quadrature digital-RF converter, and filter circuitry, consumes 50 mW and occupies a die area of 0.56 mm2 in a 0.13μm SiGe BiCMOS process.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116689972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Active On-Die Suppression of Power Supply Noise 电源噪声的主动模内抑制
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.321012
Gokce Keskin, Xin Li, L. Pileggi
{"title":"Active On-Die Suppression of Power Supply Noise","authors":"Gokce Keskin, Xin Li, L. Pileggi","doi":"10.1109/CICC.2006.321012","DOIUrl":"https://doi.org/10.1109/CICC.2006.321012","url":null,"abstract":"An active on-chip circuit is demonstrated in 130nm CMOS for the suppression of on-chip power supply noise due to power distribution resonance. Testchip measurement results indicate up to 40% reduction in power supply noise during clock/power gating at a 2% power and 6% area overhead cost. Oscillation time is reduced by 50%. Simulation results show that comparable overshoot/undershoot and ringing control via on-chip decoupling would require significantly more area and power due to leakage, particularly at 90nm and below","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114897220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Yield and Cost Modeling for 3D Chip Stack Technologies 三维芯片堆叠技术的成品率和成本建模
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320948
P. Mercier, S. R. Singh, K. Iniewski, B. Moore, P. O'Shea
{"title":"Yield and Cost Modeling for 3D Chip Stack Technologies","authors":"P. Mercier, S. R. Singh, K. Iniewski, B. Moore, P. O'Shea","doi":"10.1109/CICC.2006.320948","DOIUrl":"https://doi.org/10.1109/CICC.2006.320948","url":null,"abstract":"It has been shown that stacking a set of known good dice into a 3D chip array may be beneficial in terms of system performance and footprint area. This paper demonstrates that, in the general sense, it is also beneficial to arrange chips into a 3D stack from yield and cost perspectives. It is shown that an optimal point occurs where cost is minimized by stacking an appropriate amount of dice into a single system","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116831034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Frequency-Based Measurement of Mismatches Between Small Capacitors 基于频率的小电容失配测量
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320861
A. Verma, B. Razavi
{"title":"Frequency-Based Measurement of Mismatches Between Small Capacitors","authors":"A. Verma, B. Razavi","doi":"10.1109/CICC.2006.320861","DOIUrl":"https://doi.org/10.1109/CICC.2006.320861","url":null,"abstract":"The mismatch between two capacitors can be measured by alternately switching each into an oscillator and measuring the change in the oscillation frequency. Three-stage differential ring oscillators can provide multiple mismatch data points for capacitances as small as 8 fF. Experimental results obtained from test circuits fabricated in 0.13-mum CMOS technology also reveal lower mismatches for metal sandwich capacitors than for lateral fringe structures","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115288895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A Compact Programmable CMOS Reference With ±40μV Accuracy 一种精度为±40μV的紧凑型可编程CMOS基准
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320834
S. Venkatesh, G. Serrano, C. Twigg, P. Hasler
{"title":"A Compact Programmable CMOS Reference With ±40μV Accuracy","authors":"S. Venkatesh, G. Serrano, C. Twigg, P. Hasler","doi":"10.1109/CICC.2006.320834","DOIUrl":"https://doi.org/10.1109/CICC.2006.320834","url":null,"abstract":"A compact programmable CMOS voltage reference that is determined by the charge difference between two floating-gate transistors is introduced in this paper. A prototype circuit has been implemented in a 0.35μm CMOS process; reference voltages ranging from 50mV - 0.6V have been achieved and initial accuracy of ±40muV has been demonstrated as well. Experimental results indicate a temperature sensitivity of approximately 53μV/degC for a nominal reference voltage of 0.4V over a temperature range of -60°C to 140°C","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114671066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Low Power Approaches to High Speed CMOS Current Steering DACs 高速CMOS电流转向dac的低功耗方法
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320868
D. Mercer
{"title":"Low Power Approaches to High Speed CMOS Current Steering DACs","authors":"D. Mercer","doi":"10.1109/CICC.2006.320868","DOIUrl":"https://doi.org/10.1109/CICC.2006.320868","url":null,"abstract":"This paper discusses a number of circuit approaches which address lowering the power consumed by a modern current steering DAC while maintaining both DC and AC performance levels. An example design provides 14 bit resolution and 250 MSPS conversion rate in a 1P4M 0.18mum CMOS process, with optional 3.3 volt compatible devices. A power dissipation/conversion rate figure of merit of as low as 0.17 mW/MSPS was achieved for 1.8V operation and as low as 0.28 mW/MSPS at 3.3V. SFDR of 70 dB is achieved at a 50 MHz output frequency","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123541323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry 有时钟和无时钟数字电路产生的衬底噪声的比较和影响
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.321003
Jim Le, Christopher Hanken, Martin Held, M. Hagedorn, K. Mayaram, T. Fiez
{"title":"Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry","authors":"Jim Le, Christopher Hanken, Martin Held, M. Hagedorn, K. Mayaram, T. Fiez","doi":"10.1109/CICC.2006.321003","DOIUrl":"https://doi.org/10.1109/CICC.2006.321003","url":null,"abstract":"A pseudo-random number generator implemented in asynchronous logic generates one-fifth the RMS substrate noise compared to the equivalent design in synchronous logic. An asynchronous 8051 processor generates one-third the RMS substrate noise as the equivalent synchronous design. The SNR of a second order delta-sigma modulator (DSM) is not affected by substrate noise due to an asynchronous processor while it experiences 15 dB degradation when the synchronous 8051 processor is clocked near integer multiples of the DSM sampling frequency","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124311809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Enhancing Productivity by Continuously Improving Standard Compact Models 通过不断改进标准紧凑型车型提高生产率
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320837
J. Watts
{"title":"Enhancing Productivity by Continuously Improving Standard Compact Models","authors":"J. Watts","doi":"10.1109/CICC.2006.320837","DOIUrl":"https://doi.org/10.1109/CICC.2006.320837","url":null,"abstract":"The design of an integrated circuit requires the efforts of a large number of people with a wide range of skills. The compact model is a communication tool by which the designer of transistors, resistors and other circuit elements tells the designer of circuits how the circuit elements behave. Without this information the circuit design would be a trial and error process and modern electronics would be impossible. High quality, industry standard compact models enhance the productivity of the industry by enabling precise communication between any device design team, and any circuit design team, anywhere in the world. To be useful for leading edge design the compact model must keep up with the pace of semiconductor technology innovation. This is the great challenge for the Compact Model Council. It is only possible because the CMC creates collaboration between academics, semiconductor foundries, EDA vendors and circuit designers","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121528373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A Novel DAC Based Switching Power Amplifier for Polar Transmitter 一种新型的基于DAC的极性变送器开关功率放大器
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320851
A. Shameli, A. Safarian, A. Rofougaran, M. Rofougaran, F. D. Flaviis
{"title":"A Novel DAC Based Switching Power Amplifier for Polar Transmitter","authors":"A. Shameli, A. Safarian, A. Rofougaran, M. Rofougaran, F. D. Flaviis","doi":"10.1109/CICC.2006.320851","DOIUrl":"https://doi.org/10.1109/CICC.2006.320851","url":null,"abstract":"A novel switching power amplifier based on the concept of digital to analog converter (DAC) is presented for polar transmitter architecture. The novel idea in this amplifier is to generate a current proportional to the amplitude modulation signal and the power control bits. The current is then up-converted to the frequency of interest using switching transistors. In this paper, we demonstrate that the performance of the proposed circuit is superior compare to the existing power amplifiers designed for polar transmitter. The measurement results show maximum output power of 27.8dBm with power efficiency of 34%. Moreover, the amplifier exhibits amplitude modulation bandwidth of 4.2MHz and 62dB power control dynamic range. The circuit is fabricated in CMOS 0.18mum process with 3.3V power supply","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124058503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Determination of Power Gating Granularity for FPGA Fabric FPGA结构功率门控粒度的确定
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320938
Arifur Rahman, Satyaki Das, Tim Tuan, S. Trimberger
{"title":"Determination of Power Gating Granularity for FPGA Fabric","authors":"Arifur Rahman, Satyaki Das, Tim Tuan, S. Trimberger","doi":"10.1109/CICC.2006.320938","DOIUrl":"https://doi.org/10.1109/CICC.2006.320938","url":null,"abstract":"In this study, we present a design methodology to determine the granularity of power gating for field programmable gate arrays (FPGAs). Fine-grain power gating is more effective than coarse-grain power gating to reduce the active leakage power of unused logic and interconnection resources. However, the area overhead in fine-grain power gating is higher than that of coarse-grain power gating. Based on the placement and routing of benchmark designs in Spartan-3trade-like FPGA, guidelines for determining the granularity of power gating are provided. It is found that programmable resources with low utilization can be power gated more coarsely than the resources with high utilization","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129864608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
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