发布求助
文献互助 智能选刊 最新文献

IEEE Custom Integrated Circuits Conference 2006最新文献

筛选
英文 中文
Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices 45纳米以下CMOS器件的电特性波动
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320881
Fu-Liang Yang, Jiunn-Ren Hwang, Yiming Li
{"title":"Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices","authors":"Fu-Liang Yang, Jiunn-Ren Hwang, Yiming Li","doi":"10.1109/CICC.2006.320881","DOIUrl":"https://doi.org/10.1109/CICC.2006.320881","url":null,"abstract":"Random fluctuations of electrical characteristics in sub-45nm CMOS devices introduced by process-parameter variations through severe short channel effects have made the scaling of conventional planar transistors much more difficult than ever before, especially while further reduction of gate dielectric thickness is ambiguous. In this paper, the authors systematically investigate the fluctuations of threshold voltages at varied gate length, considering the effects of channel doping, gate dielectric thickness, and new transistor structures such as thin-buried-oxide SOI and FinFETs. Quantitative analysis is undertaken in terms of three major variation sources: random doping distribution, gate length deviation, and line edge roughness. The analysis also features a low Vt-fluctuation transistor for 16nm node achieved with undoped body, mid-gap metal gate, and nanowire channel","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129379517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
High-Temperature, High Reliability EEPROM Design For Automotive Applications 高温、高可靠性汽车EEPROM设计
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320818
J. Walsh, G. Scott
{"title":"High-Temperature, High Reliability EEPROM Design For Automotive Applications","authors":"J. Walsh, G. Scott","doi":"10.1109/CICC.2006.320818","DOIUrl":"https://doi.org/10.1109/CICC.2006.320818","url":null,"abstract":"An EEPROM has been developed capable of extreme temperature ranges not currently available in the industry. The memory is expected to handle 100K write cycles, 10K of which can be at 175C. To accommodate the reliable operation at the extreme temperature and write-cycle conditions without adding steps to the base process, several cell and system level design techniques were implemented including a differential bit architecture, time and temperature program voltage shaping","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116616915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
EDA Challenges in Nano-scale Technology 纳米级技术中的EDA挑战
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320844
J. Kawa, C. Chiang, R. Camposano
{"title":"EDA Challenges in Nano-scale Technology","authors":"J. Kawa, C. Chiang, R. Camposano","doi":"10.1109/CICC.2006.320844","DOIUrl":"https://doi.org/10.1109/CICC.2006.320844","url":null,"abstract":"Since the onset of the 90 nm node the challenges associated with further transistor scaling while maintaining a consistently functional, reliable, and yielding design have increased substantially. While those challenges carry across the spectrum of the manufacturing, the EDA, and the design communities, we believe it is the responsibility and the goal of the EDA industry to deal with those issues as thoroughly and as seamlessly as possible to make those challenges transparent to the designer. In this paper we expose and analyze a plurality of those challenges and briefly go over the solutions EDA tools are offering for dealing with them. We also look forward and cover some of the future challenges associated with the integration of the emerging bottoms-up nano-materials flow with the traditional CMOS top-down process flow which has also entered the nano-era","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121819864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
An Energy Scalable Computational Array for Sensor Signal Processing 用于传感器信号处理的能量可扩展计算阵列
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320900
Liping Guo, M. Scott, R. Amirtharajah
{"title":"An Energy Scalable Computational Array for Sensor Signal Processing","authors":"Liping Guo, M. Scott, R. Amirtharajah","doi":"10.1109/CICC.2006.320900","DOIUrl":"https://doi.org/10.1109/CICC.2006.320900","url":null,"abstract":"Harvesting energy from environmental sources can extend wireless sensor network node lifetime beyond the limits of battery technology. However, the output power from an energy harvester is highly variable. We propose a domain-specific computational array which maximizes sensor performance by matching system power consumption to the available scavenged energy through power scalable approximate signal processing. The array consists of distributed arithmetic (DA) based functional units coupled with a reconfigurable interconnect structure. Each unit implements several core linear and nonlinear signal processing functions in an area efficient manner which also minimizes leakage power. Several sensor DSP applications (FIR, IIR, and FFT) have been mapped onto the array. Post-layout simulations confirm that the proposed domain-specific computational array is energy efficient and energy scalable","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122206728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 50-GHz Phase-Locked Loop in 130-nm CMOS 130nm CMOS中的50ghz锁相环
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320940
C. Cao, Yanping Ding, K. O. Kenneth
{"title":"A 50-GHz Phase-Locked Loop in 130-nm CMOS","authors":"C. Cao, Yanping Ding, K. O. Kenneth","doi":"10.1109/CICC.2006.320940","DOIUrl":"https://doi.org/10.1109/CICC.2006.320940","url":null,"abstract":"A 50-GHz charge pump phase locked loop (PLL) utilizing an LC-oscillator based injection locked divider is fabricated in a 130-nm logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The circuit including buffers consumes 57 mW from 1.5/0.8 V supplies. The phase noise at 50 kHz, 1 MHz and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs -22-dBm second order harmonic frequencies between 91.8 and 101 GHz","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123958349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique 一种100 ms /s 4 mhz带宽77.3 db SNDR ΔΣ三采样ADC
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320962
Y. Kanazawa, Y. Fujimoto, Pascal Lo Ré, M. Miyamoto
{"title":"A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique","authors":"Y. Kanazawa, Y. Fujimoto, Pascal Lo Ré, M. Miyamoto","doi":"10.1109/CICC.2006.320962","DOIUrl":"https://doi.org/10.1109/CICC.2006.320962","url":null,"abstract":"A new ΔΣ ADC architecture using a triple sampling technique and a two-step summation scheme is presented. A 4th-order switched-capacitor ΔΣ ADC with a 4-bit quantizer is designed for a low-power direct-conversion digital TV receiver SoC. It achieves a 77.3-dB SNDR over a 4-MHz bandwidth with a 100-MHz clock frequency. The chip, fabricated in a 0.18-mum CMOS process, occupies 1.57 mm2 and draws 15.3 mA from a 1.8-V supply. It achieves a 0.58-pJ/conversion FOM","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130466411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver 采用全差分脉冲接收机的36Gb/s ACCI多通道总线
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320976
L. Luo, John M. Wilson, S. Mick, Jian Xu, L. Zhang, E. Erickson, P. Franzon
{"title":"A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver","authors":"L. Luo, John M. Wilson, S. Mick, Jian Xu, L. Zhang, E. Erickson, P. Franzon","doi":"10.1109/CICC.2006.320976","DOIUrl":"https://doi.org/10.1109/CICC.2006.320976","url":null,"abstract":"A new differential pulse receiver is demonstrated for AC coupled interconnect (ACCI), which enables the highest data rate, at 6Gb/s/channel (36Gb/s aggregate), for capacitively coupled systems using pulse signaling. The system works across FR4 printed circuit board (PCB) interconnect lengths of up to 30cm with coupling capacitors from 95fF to 165fF, while dissipating only 1.97mW/Gbps for the entire differential transceiver (0.83pJ/bit for the transmitter and 1.23pJ/bit for the receiver)","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126484859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End 高IIP3电流模式RF CMOS前端的共门变压器反馈LNA
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320941
A. Liscidini, Cesare Ghezzi, Emanuele Depaoli, G. Albasini, I. Bietti, R. Castello
{"title":"Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End","authors":"A. Liscidini, Cesare Ghezzi, Emanuele Depaoli, G. Albasini, I. Bietti, R. Castello","doi":"10.1109/CICC.2006.320941","DOIUrl":"https://doi.org/10.1109/CICC.2006.320941","url":null,"abstract":"A new topology of transformer based low noise amplifier is presented. The structure realizes a low noise input match and a current gain greater than one by a current to current positive feedback closed around a common gate stage. The amplifier is inserted in a high linearity current mode RF front-end receiver working between 4.15-4.4GHz with a NF of 4.2dB, a gain of 24.2dB and an IIP3 of -2dBm","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128954190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS 基于0.18μm CMOS的10Gbps突发模式CDR电路
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320828
Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
{"title":"A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS","authors":"Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu","doi":"10.1109/CICC.2006.320828","DOIUrl":"https://doi.org/10.1109/CICC.2006.320828","url":null,"abstract":"A 10Gbps burst-mode clock and data recovery (CDR) circuit has been fabricated in 0.18mum CMOS technology. It recovers the input data and clock within 32 bits by using a gated voltage-controlled oscillator, a quadrature generator and a phase-aligning loop incorporating a half-rate bang-bang phase detector and a digital phase interpolator. The measured peak-to-peak jitter of the recovered clock is 10.44ps. The die area is 1.73 times 2.01 mm2 and draw 200mW from a 1.8V supply.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117101698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement 提高良率的CMOS混合信号电路工艺变化灵敏度表征
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320950
Daeik D. Kim, Choongyeun Cho, Jonghae Kim, J. Plouchart, R. Trzcinski, D. Ahlgren
{"title":"CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement","authors":"Daeik D. Kim, Choongyeun Cho, Jonghae Kim, J. Plouchart, R. Trzcinski, D. Ahlgren","doi":"10.1109/CICC.2006.320950","DOIUrl":"https://doi.org/10.1109/CICC.2006.320950","url":null,"abstract":"A mixed-signal circuit's performance and yield dependency on process variation are investigated with numerical circuit solution, statistical simulation, and implemented circuit measurement in 65nm partially-depleted silicon-on-insulator CMOS process. Increased relative variation in 65nm process is examined with site-to-site and wafer-to-wafer process variations. A current-controlled oscillator's performance and device threshold voltages are cross-correlated using simulation and RF measurement. Up to 93.9% cross-correlation between oscillation frequency and device threshold voltage is obtained, and strong model-to-hardware correlation is observed through statistical analysis of simulation result and circuit measurement. The yield learning process of design, simulation, measurement, and statistical analysis is proposed","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117337787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信