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IEEE Custom Integrated Circuits Conference 2006最新文献

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A 300 °C, 110-dB Sigma-Delta Modulator with Programmable Gain in Bulk CMOS 具有可编程增益的300°C, 110 db Sigma-Delta调制器
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320943
Xinyu Yu, S. Garverick
{"title":"A 300 °C, 110-dB Sigma-Delta Modulator with Programmable Gain in Bulk CMOS","authors":"Xinyu Yu, S. Garverick","doi":"10.1109/CICC.2006.320943","DOIUrl":"https://doi.org/10.1109/CICC.2006.320943","url":null,"abstract":"A bulk CMOS, switched-capacitor 2nd-order sigma-delta modulator with pre-amplification uses correlated double sampling, constant-gm biasing, and a modulator architecture with coefficients adjusted to improve temperature stability. The stand-alone sigma-delta modulator has a peak SNR and SNDR ges 94 dB and 87 dB, respectively, for temperature from 25 degC to 300 degC with an oversampling ratio of 256. Including the preamplifier, the modulator dynamic range is ges 110 dB at temperatures up to 300 degC","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132765756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 14mW 2.5MS/s 14bit Sigma-Delta Modulator Using Pseudo-Differential Split-Path Cascode Amplifiers 基于伪差分分路级联码放大器的14mW 2.5MS/s 14bit Sigma-Delta调制器
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320961
Z. Cao, Tongyu Song, Shouli Yan
{"title":"A 14mW 2.5MS/s 14bit Sigma-Delta Modulator Using Pseudo-Differential Split-Path Cascode Amplifiers","authors":"Z. Cao, Tongyu Song, Shouli Yan","doi":"10.1109/CICC.2006.320961","DOIUrl":"https://doi.org/10.1109/CICC.2006.320961","url":null,"abstract":"Switched-capacitor biased pseudo-differential split-path cascode amplifiers are proposed to achieve high power efficiency and small die area for a 14-bit 2.5MS/s DeltaSigma modulator. Sufficient power supply rejection is maintained through the biasing circuit. A novel signal and reference sampling network eliminates input common-mode voltages and relaxes op-amp linearity requirements, making it possible to use short channel length transistors for speed and power efficiency. A prototype chip is fabricated in a 0.25mum CMOS technology with a core area of 0.27mm2. Experimental results show that 84dB dynamic range is achieved with the 1.25MHz signal bandwidth when clocked at 120MHz. The power dissipation is 14mW at 2.5V including the on-chip voltage reference buffers","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131743955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 1.5-V CMOS Receiver Front-End for 9-Band MB-OFDM UWB System 用于9波段MB-OFDM UWB系统的1.5 v CMOS接收器前端
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.321000
S. Lou, Hui Zheng, H. Luong
{"title":"A 1.5-V CMOS Receiver Front-End for 9-Band MB-OFDM UWB System","authors":"S. Lou, Hui Zheng, H. Luong","doi":"10.1109/CICC.2006.321000","DOIUrl":"https://doi.org/10.1109/CICC.2006.321000","url":null,"abstract":"This paper presents the design of a CMOS receiver front-end (RFE) with dual-conversion zero-IF architecture for multi-band OFDM (MB-OFDM) system covering the first 9 frequency bands from 3.1 GHz to 8.0 GHz, each with a bandwidth of 528 MHz. A 3-stage wideband variable-gain LNA and a novel mixer with bottom LO input devices are proposed. A fully integrated frequency synthesizer is included to generate the desired LO signals with a band switching time of less than Ins. Fabricated in TSMC 0.18mum CMOS process and operated at 1.5 V, the RFE measures a maximum noise figure of 8.1 dB and an in-band IIP3 of -11.1 dBm while consuming a total current of 81.5 mA","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134372009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Inductor- and Transformer-based Integrated RF Oscillators: A Comparative Study 基于电感和变压器的集成射频振荡器:比较研究
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320954
H. Krishnaswamy, H. Hashemi
{"title":"Inductor- and Transformer-based Integrated RF Oscillators: A Comparative Study","authors":"H. Krishnaswamy, H. Hashemi","doi":"10.1109/CICC.2006.320954","DOIUrl":"https://doi.org/10.1109/CICC.2006.320954","url":null,"abstract":"Prior publications claim that transformer-based resonators achieve improvements in quality factor (Q), which translates to better phase noise in oscillators. This paper combines rigorous analysis with on-chip practical considerations for various types of on-chip transformers to demonstrate the importance of the resonator topology for Q-enhancement. We show that for a fixed silicon chip area, transformer-based resonators do not exhibit superior performance compared to inductor-based designs. Prototype oscillators are implemented at 5GHz in a 0.18mum CMOS process to validate these claims","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130994860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Implications of Proximity Effects for Analog Design 接近效应对模拟设计的影响
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320869
P. Drennan, M. Kniffin, David R. Locascio
{"title":"Implications of Proximity Effects for Analog Design","authors":"P. Drennan, M. Kniffin, David R. Locascio","doi":"10.1109/CICC.2006.320869","DOIUrl":"https://doi.org/10.1109/CICC.2006.320869","url":null,"abstract":"This paper addresses two significant proximity effects, well proximity and STI stress, as they relate to analog circuit design. Device performance is impacted by layout features located near, but not part of the device. This adds new complexities to analog design. In either case, bias points can shift by 20-30%, causing potentially catastrophic failures in circuits. We show, for the first time, that a MOSFET placed close to a well-edge creates a graded channel","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132574688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 105
Fully-Integrated CMOS Power Regulator for Telemetry-Powered Implantable Biomedical Microsystems 用于遥测供电的植入式生物医学微系统的全集成CMOS功率调节器
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320862
A. M. Sodagar, K. Najafi, K. Wise, Maysam Ghovanloo
{"title":"Fully-Integrated CMOS Power Regulator for Telemetry-Powered Implantable Biomedical Microsystems","authors":"A. M. Sodagar, K. Najafi, K. Wise, Maysam Ghovanloo","doi":"10.1109/CICC.2006.320862","DOIUrl":"https://doi.org/10.1109/CICC.2006.320862","url":null,"abstract":"This paper reports a fully-integrated multi-output CMOS power regulator designed for telemetry-powered implantable microsystems. It is comprised of a CMOS full-wave bridge rectifier, a wide-range multi-output voltage reference and DC level shifter circuits, and three linear voltage regulators. The power regulator fabricated in a 1.5mum standard CMOS process, provides 5V, 3V, and 1.5V regulated outputs, exhibits load regulation factor of as low as 5% when delivering up to 17.3mA load current, and demonstrates line regulation factor of as low as 0.3%/V over 1.8-V input amplitude variation","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"444 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125845025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading 900MHz至1.2GHz两相谐振时钟网络与可编程的驱动程序和加载
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320995
Juang-Ying Chueh, V. Sathe, M. Papaefthymiou
{"title":"900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading","authors":"Juang-Ying Chueh, V. Sathe, M. Papaefthymiou","doi":"10.1109/CICC.2006.320995","DOIUrl":"https://doi.org/10.1109/CICC.2006.320995","url":null,"abstract":"A resonant clock network with programmable driver and loading is designed in a 0.13mum CMOS technology. The 2mm times 2mm distribution network has on-chip inductors and performs a forced oscillation at the rate of a reference clock programmable in the 900MHz to 1.2GHz range. Clock amplitude and energy efficiency trade-offs at and off resonance are explored with various driver configurations. Energy efficiency per cycle is 1.39 to 1.56 times greater than previous resonant distribution networks","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115513318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme 使用纠错匹配方案的软容错内容可寻址存储器(CAM)
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320887
K. Pagiamtzis, N. Azizi, F. Najm
{"title":"A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme","authors":"K. Pagiamtzis, N. Azizi, F. Najm","doi":"10.1109/CICC.2006.320887","DOIUrl":"https://doi.org/10.1109/CICC.2006.320887","url":null,"abstract":"Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred to as single-event upsets (SEUs), will become more problematic in future technologies. This paper presents a binary content-addressable memory (CAM) design with high immunity to SEUs. Conventionally, error-correcting codes (ECC) have been used in SRAMs to address this issue, but these techniques are not immediately applicable to CAMs because they depend on processing the full contents of the memory word outside the array, which is not possible in a normal CAM access. The proposed design consists of a new matching technique that uses coding to increase the Hamming distance between words, in conjunction with a modified matchline sensing scheme. The result is a CAM design that reduces the SER with no increase in delay or power dissipation, and with only a 12% increase in area","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114932848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
A 0.9-V Double-Balanced Quadrature-Input Quadrature-Output Frequency Divider 0.9 v双平衡正交输入正交输出分频器
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320959
Hui Zheng, H. Luong
{"title":"A 0.9-V Double-Balanced Quadrature-Input Quadrature-Output Frequency Divider","authors":"Hui Zheng, H. Luong","doi":"10.1109/CICC.2006.320959","DOIUrl":"https://doi.org/10.1109/CICC.2006.320959","url":null,"abstract":"A double-balanced quadrature-input quadrature-output (QIQO) divider is proposed. By making use of the quadrature phase outputs from a quadrature VCO (QVCO) or the other quadrature signal generator, the proposed QIQO divider provides a mechanism to achieve an output IQ phase sequence that is inherently tracked with the input IQ phase sequence. Moreover, compared with conventional dividers, the QIQO divider not only provides smaller and better-matched input loading to the QVCO but also improved quadrature phase accuracy for both QVCO and the divider itself. Fabricated in a 0.18-mum CMOS process and operated at 0.9 V, the QIQO divider measures an image rejection of -62 dBc while consuming 7.2 mW","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"21 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129699962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 2.4GHz direct modulated 0.18μm CMOS IEEE 802.15.4 compliant Transmitter for ZigBee 2.4GHz直调0.18μm CMOS IEEE 802.15.4兼容ZigBee发射机
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320847
S. Beyer, R. Jaehne, W. Kluge, D. Eggert
{"title":"A 2.4GHz direct modulated 0.18μm CMOS IEEE 802.15.4 compliant Transmitter for ZigBee","authors":"S. Beyer, R. Jaehne, W. Kluge, D. Eggert","doi":"10.1109/CICC.2006.320847","DOIUrl":"https://doi.org/10.1109/CICC.2006.320847","url":null,"abstract":"This paper presents improved fractional-N based transmitter architecture, fully compliant with ZigBee IEEE 802.15.4 standard. Operating in the 2.4 GHz ISM frequency range, the fractional-N PLL based synthesizer architecture achieves an integrated phase noise of 2.6 deg rms (250 Hz - 1.5 MHz). The transmitter error-vector magnitude (EVM) for MSK modulated signals is 5.3 % with an output level of approximately +4 dBm. This transmitter is incorporated in a single-chip RF transceiver providing a complete antenna-to-micro controller radio interface","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130629420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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