A 50-GHz Phase-Locked Loop in 130-nm CMOS

Abstract

A 50-GHz charge pump phase locked loop (PLL) utilizing an LC-oscillator based injection locked divider is fabricated in a 130-nm logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The circuit including buffers consumes 57 mW from 1.5/0.8 V supplies. The phase noise at 50 kHz, 1 MHz and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs -22-dBm second order harmonic frequencies between 91.8 and 101 GHz