A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique

IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI:10.1109/CICC.2006.320962

Y. Kanazawa, Y. Fujimoto, Pascal Lo Ré, M. Miyamoto

引用次数: 12

Abstract

A new ΔΣ ADC architecture using a triple sampling technique and a two-step summation scheme is presented. A 4th-order switched-capacitor ΔΣ ADC with a 4-bit quantizer is designed for a low-power direct-conversion digital TV receiver SoC. It achieves a 77.3-dB SNDR over a 4-MHz bandwidth with a 100-MHz clock frequency. The chip, fabricated in a 0.18-mum CMOS process, occupies 1.57 mm2 and draws 15.3 mA from a 1.8-V supply. It achieves a 0.58-pJ/conversion FOM

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一种100 ms /s 4 mhz带宽77.3 db SNDR ΔΣ三采样ADC

提出了一种采用三重采样技术和两步求和的新型ΔΣ ADC结构。设计了一种带4位量化器的4阶开关电容ΔΣ ADC，用于低功耗直接转换数字电视接收器SoC。在100 mhz时钟频率下，在4 mhz带宽上实现77.3 db SNDR。该芯片采用0.18 μ m CMOS工艺制造，占地1.57 mm2，从1.8 v电源输出15.3 mA。它实现了0.58 pj /转换FOM

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Custom Integrated Circuits Conference 2006

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