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IEEE Custom Integrated Circuits Conference 2006最新文献

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Analysis of Oscillators Locked by Large Injection Signals: Generalized Adler's Equation and Geometrical Interpretation 大注入信号锁住振子的分析:广义Adler方程及其几何解释
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320928
A. Mirzaei, M. E. Heidari, A. Abidi
{"title":"Analysis of Oscillators Locked by Large Injection Signals: Generalized Adler's Equation and Geometrical Interpretation","authors":"A. Mirzaei, M. E. Heidari, A. Abidi","doi":"10.1109/CICC.2006.320928","DOIUrl":"https://doi.org/10.1109/CICC.2006.320928","url":null,"abstract":"Using the hard-limiting characteristics of transconductors, a new model for injection-locking, applicable for any strong and weak injection, is proposed. Backed by simulations, examples of the powerfulness of this new model are enumerated as proof of the concept.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134252406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
Rigorous Analytical/Graphical Injection Locking Analysis of Two-Port Negative Resistance Oscillators 双端口负电阻振荡器的严格解析/图形注入锁定分析
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320965
Ting Mei, J. Roychowdhury
{"title":"Rigorous Analytical/Graphical Injection Locking Analysis of Two-Port Negative Resistance Oscillators","authors":"Ting Mei, J. Roychowdhury","doi":"10.1109/CICC.2006.320965","DOIUrl":"https://doi.org/10.1109/CICC.2006.320965","url":null,"abstract":"In this paper, the authors present a simple but rigorous nonlinear analysis for understanding and predicting steady-state operation and injection locking in two-port nonlinear negative-resistance oscillators (such as the Colpitts, Pierce, etc., topologies commonly used in RFICs). Key advances of our approach include the use of vector-based nonlinear feedback analysis and treatment of amplitude and frequency components in a coupled way. The authors develop rigorous and insightful graphical approaches for output voltage estimation and injection lock range prediction. The authors validate the analytical approach against transient and harmonic balance simulations","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"118 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133356211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Compact Programmable CMOS Reference With ±40μV Accuracy 一种精度为±40μV的紧凑型可编程CMOS基准
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320834
S. Venkatesh, G. Serrano, C. Twigg, P. Hasler
{"title":"A Compact Programmable CMOS Reference With ±40μV Accuracy","authors":"S. Venkatesh, G. Serrano, C. Twigg, P. Hasler","doi":"10.1109/CICC.2006.320834","DOIUrl":"https://doi.org/10.1109/CICC.2006.320834","url":null,"abstract":"A compact programmable CMOS voltage reference that is determined by the charge difference between two floating-gate transistors is introduced in this paper. A prototype circuit has been implemented in a 0.35μm CMOS process; reference voltages ranging from 50mV - 0.6V have been achieved and initial accuracy of ±40muV has been demonstrated as well. Experimental results indicate a temperature sensitivity of approximately 53μV/degC for a nominal reference voltage of 0.4V over a temperature range of -60°C to 140°C","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114671066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers 一种用于背板收发器的5Gb/s反射消除发射器
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320985
R. Yuen, Marcus van Ierssel, A. Sheikholeslami, W. Walker, H. Tamura
{"title":"A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers","authors":"R. Yuen, Marcus van Ierssel, A. Sheikholeslami, W. Walker, H. Tamura","doi":"10.1109/CICC.2006.320985","DOIUrl":"https://doi.org/10.1109/CICC.2006.320985","url":null,"abstract":"We present a 5Gb/s transmitter that cancels the reflected signals from any impedance discontinuity located at up to 64UI away from the transmitter and spread over 8UI interval. Measured results from our 0.11mum CMOS design reveal a 150mV eye-opening, from a nearly closed eye, when reflection cancellation is activated. The design consumes 510muA for the PLL operation, 60mA for data generation, and 50mA for data transmission, all from a 1.2V supply","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"31 40","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113941301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Frequency-Based Measurement of Mismatches Between Small Capacitors 基于频率的小电容失配测量
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320861
A. Verma, B. Razavi
{"title":"Frequency-Based Measurement of Mismatches Between Small Capacitors","authors":"A. Verma, B. Razavi","doi":"10.1109/CICC.2006.320861","DOIUrl":"https://doi.org/10.1109/CICC.2006.320861","url":null,"abstract":"The mismatch between two capacitors can be measured by alternately switching each into an oscillator and measuring the change in the oscillation frequency. Three-stage differential ring oscillators can provide multiple mismatch data points for capacitances as small as 8 fF. Experimental results obtained from test circuits fabricated in 0.13-mum CMOS technology also reveal lower mismatches for metal sandwich capacitors than for lateral fringe structures","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115288895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 10-bit 1GSample/s DAC in 90nm CMOS for Embedded Applications 用于嵌入式应用的10位1GSample/s的90纳米CMOS DAC
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320871
Jing Cao, Haiqing Lin, Y. Xiang, Chun-Fu Kao, K. Dyer
{"title":"A 10-bit 1GSample/s DAC in 90nm CMOS for Embedded Applications","authors":"Jing Cao, Haiqing Lin, Y. Xiang, Chun-Fu Kao, K. Dyer","doi":"10.1109/CICC.2006.320871","DOIUrl":"https://doi.org/10.1109/CICC.2006.320871","url":null,"abstract":"A 90 nm CMOS 10-bit 1 GS/s current-steering D/A converter is presented. It is designed and optimized for next generation high-speed digital communication SoCs. With only five power/ground pins and a 10-bit architecture, 72 dB SFDR and 9.2 ENOB are measured with a full-scale 41.3 MHz input at 800 MS/s. At 1.05 GS/s, 68 dB SFDR is achieved for a full-scale 54.3 MHz input. It dissipates a core power of 49 mW, the lowest power consumption reported at this performance level, and occupies a die area of merely 0.36 mm2. The monolithic DAC is fabricated in TSMC 1P9M 90nm CMOS process","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124509880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Low Power Approaches to High Speed CMOS Current Steering DACs 高速CMOS电流转向dac的低功耗方法
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320868
D. Mercer
{"title":"Low Power Approaches to High Speed CMOS Current Steering DACs","authors":"D. Mercer","doi":"10.1109/CICC.2006.320868","DOIUrl":"https://doi.org/10.1109/CICC.2006.320868","url":null,"abstract":"This paper discusses a number of circuit approaches which address lowering the power consumed by a modern current steering DAC while maintaining both DC and AC performance levels. An example design provides 14 bit resolution and 250 MSPS conversion rate in a 1P4M 0.18mum CMOS process, with optional 3.3 volt compatible devices. A power dissipation/conversion rate figure of merit of as low as 0.17 mW/MSPS was achieved for 1.8V operation and as low as 0.28 mW/MSPS at 3.3V. SFDR of 70 dB is achieved at a 50 MHz output frequency","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123541323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A Fully-Integrated 0.11μm CMOS Digital Low-IF DVB-S2 Satellite TV Dual Tuner SOC 全集成0.11μm CMOS数字低中频DVB-S2卫星电视双调谐器SOC
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.321011
A. Maxim, R. Poorfard, R. Johnson, P. Crawley, J. Kao, Z. Dong, M. Chennam, T. Nutt, D. Trager
{"title":"A Fully-Integrated 0.11μm CMOS Digital Low-IF DVB-S2 Satellite TV Dual Tuner SOC","authors":"A. Maxim, R. Poorfard, R. Johnson, P. Crawley, J. Kao, Z. Dong, M. Chennam, T. Nutt, D. Trager","doi":"10.1109/CICC.2006.321011","DOIUrl":"https://doi.org/10.1109/CICC.2006.321011","url":null,"abstract":"A digital low-IF fully-integrated dual tuner for DVB-S2 satellite TV applications was realized in 0.11μm CMOS. It provides baseband digital I/Q outputs for a demodulator-on-host back-end processor. A wide bandwidth ring oscillator based frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a sliding low-IF frequency, while the second down-conversion to baseband was performed in the digital domain. The low-IF architecture allows a discrete AGC loop, while avoiding 1/f noise and DC offset issues. Eliminating the VCO tank inductors minimizes frequency pulling and parasitic coupling to front-end LNA, allowing the integration of a large digital core on the same die with the sensitive RF front-end.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122707479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Determination of Power Gating Granularity for FPGA Fabric FPGA结构功率门控粒度的确定
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320938
Arifur Rahman, Satyaki Das, Tim Tuan, S. Trimberger
{"title":"Determination of Power Gating Granularity for FPGA Fabric","authors":"Arifur Rahman, Satyaki Das, Tim Tuan, S. Trimberger","doi":"10.1109/CICC.2006.320938","DOIUrl":"https://doi.org/10.1109/CICC.2006.320938","url":null,"abstract":"In this study, we present a design methodology to determine the granularity of power gating for field programmable gate arrays (FPGAs). Fine-grain power gating is more effective than coarse-grain power gating to reduce the active leakage power of unused logic and interconnection resources. However, the area overhead in fine-grain power gating is higher than that of coarse-grain power gating. Based on the placement and routing of benchmark designs in Spartan-3trade-like FPGA, guidelines for determining the granularity of power gating are provided. It is found that programmable resources with low utilization can be power gated more coarsely than the resources with high utilization","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129864608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology 采用0.13 μm CMOS技术的30-GS/秒跟踪保持放大器
IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI: 10.1109/CICC.2006.320891
S. Shahramian, S. Voinigescu, A. C. Carusone
{"title":"A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology","authors":"S. Shahramian, S. Voinigescu, A. C. Carusone","doi":"10.1109/CICC.2006.320891","DOIUrl":"https://doi.org/10.1109/CICC.2006.320891","url":null,"abstract":"A 30-GS/sec CMOS track and hold amplifier (THA) is designed and fabricated in a 0.13-μm technology. The chip operates from a 1.8-V supply and consumes 270 mW. The THA employs a low noise TIA input stage and a switched source follower (SSF) track and hold block. The SSF topology overcomes the shortcomings of switched series transistors by eliminating the use of a series switch all together. The measured single-ended S-parameters show an input and output return loss of better than -10 dB up to 35 GHz and 7 GHz of bandwidth when the circuit is operated in track mode. The measured total harmonic distortion of the THA is better than -29 dB.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131322900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
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