具有电容耦合的低抖动多相锁相环

IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI:10.1109/CICC.2006.320968

Junyoung Park, M. Flynn

{"title":"具有电容耦合的低抖动多相锁相环","authors":"Junyoung Park, M. Flynn","doi":"10.1109/CICC.2006.320968","DOIUrl":null,"url":null,"abstract":"Capacitive coupling improves both phase noise and phase accuracy in coupled LC oscillators since the coupling current is in phase with the regeneration current. A prototype 3 GHz PLL with four LC oscillator stages and capacitive coupling is fabricated in 0.13mum CMOS. The long term measured RMS jitter of the buffered clock from the PLL is 1.61ps and the pk-pk jitter is 13.33ps","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A Low Jitter Multi-Phase PLL with Capacitive Coupling\",\"authors\":\"Junyoung Park, M. Flynn\",\"doi\":\"10.1109/CICC.2006.320968\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Capacitive coupling improves both phase noise and phase accuracy in coupled LC oscillators since the coupling current is in phase with the regeneration current. A prototype 3 GHz PLL with four LC oscillator stages and capacitive coupling is fabricated in 0.13mum CMOS. The long term measured RMS jitter of the buffered clock from the PLL is 1.61ps and the pk-pk jitter is 13.33ps\",\"PeriodicalId\":269854,\"journal\":{\"name\":\"IEEE Custom Integrated Circuits Conference 2006\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Custom Integrated Circuits Conference 2006\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2006.320968\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Custom Integrated Circuits Conference 2006","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2006.320968","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

电容耦合提高了耦合LC振荡器的相位噪声和相位精度，因为耦合电流与再生电流是同相的。在0.13 μ m CMOS上制作了一个具有4级LC振荡器和电容耦合的3ghz锁相环原型。来自锁相环的缓冲时钟的长期测量有效值抖动为1.61ps, pk-pk抖动为13.33ps

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A Low Jitter Multi-Phase PLL with Capacitive Coupling

Capacitive coupling improves both phase noise and phase accuracy in coupled LC oscillators since the coupling current is in phase with the regeneration current. A prototype 3 GHz PLL with four LC oscillator stages and capacitive coupling is fabricated in 0.13mum CMOS. The long term measured RMS jitter of the buffered clock from the PLL is 1.61ps and the pk-pk jitter is 13.33ps

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE Custom Integrated Circuits Conference 2006

自引率

0.00%

发文量