有时钟和无时钟数字电路产生的衬底噪声的比较和影响

IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI:10.1109/CICC.2006.321003

Jim Le, Christopher Hanken, Martin Held, M. Hagedorn, K. Mayaram, T. Fiez

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引用次数: 5

摘要

在异步逻辑中实现的伪随机数发生器产生的RMS基板噪声与同步逻辑中的等效设计相比减少了五分之一。异步8051处理器产生的RMS基板噪声是等效同步设计的三分之一。二阶δ - σ调制器(DSM)的信噪比不受异步处理器引起的衬底噪声的影响，而当同步8051处理器的时钟接近DSM采样频率的整数倍时，其信噪比会下降15 dB

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Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry

A pseudo-random number generator implemented in asynchronous logic generates one-fifth the RMS substrate noise compared to the equivalent design in synchronous logic. An asynchronous 8051 processor generates one-third the RMS substrate noise as the equivalent synchronous design. The SNR of a second order delta-sigma modulator (DSM) is not affected by substrate noise due to an asynchronous processor while it experiences 15 dB degradation when the synchronous 8051 processor is clocked near integer multiples of the DSM sampling frequency

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IEEE Custom Integrated Circuits Conference 2006

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