FPGA结构功率门控粒度的确定

Arifur Rahman, Satyaki Das, Tim Tuan, S. Trimberger
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引用次数: 44

摘要

在这项研究中,我们提出了一种设计方法来确定现场可编程门阵列(fpga)的功率门控粒度。细粒度功率门控比粗粒度功率门控更能有效地降低未使用的逻辑资源和互连资源的有源泄漏功率。但细粒功率门控的面积开销比粗粒功率门控大。基于类似spartan -3trade的FPGA中基准设计的放置和路由,给出了确定功率门控粒度的准则。研究发现,低利用率的可编程资源比高利用率的可编程资源可以更粗地进行功率门控
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Determination of Power Gating Granularity for FPGA Fabric
In this study, we present a design methodology to determine the granularity of power gating for field programmable gate arrays (FPGAs). Fine-grain power gating is more effective than coarse-grain power gating to reduce the active leakage power of unused logic and interconnection resources. However, the area overhead in fine-grain power gating is higher than that of coarse-grain power gating. Based on the placement and routing of benchmark designs in Spartan-3trade-like FPGA, guidelines for determining the granularity of power gating are provided. It is found that programmable resources with low utilization can be power gated more coarsely than the resources with high utilization
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