2017 IEEE International Solid-State Circuits Conference (ISSCC)最新文献_第8页

5.3 A 95µW 24MHz digitally controlled crystal oscillator for IoT applications with 36nJ start-up energy and >13× start-up time reduction using a fully-autonomous dynamically-adjusted load 5.3一个95µW 24MHz数字控制晶体振荡器，用于物联网应用，使用全自动动态调节负载，启动能量36nJ，启动时间减少>13倍

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870275

M. Ding, Yao-Hong Liu, Yan Zhang, Chuang Lu, P. Zhang, B. Busze, Christian Bachmann, K. Philips

引用次数: 23

29.3 A 40Gb/s PAM-4 transmitter based on a ring-resonator optical DAC in 45nm SOI CMOS 29.3基于45nm SOI CMOS环形谐振光DAC的40Gb/s PAM-4发射机

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870473

S. Moazeni, Sen Lin, M. Wade, L. Alloatti, Rajeev J Ram, M. Popović, V. Stojanović

引用次数: 11

22.4 A reconfigurable bidirectional wireless power transceiver with maximum-current charging mode and 58.6% battery-to-battery efficiency 22.4可重构双向无线电源收发器，最大电流充电模式，电池对电池效率58.6%

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870418

Mo Huang, Yan Lu, U. Seng-Pan, R. Martins

引用次数: 18

27.7 A 30.5mm3 fully packaged implantable device with duplex ultrasonic data and power links achieving 95kb/s with <10−4 BER at 8.5cm depth 27.7 30.5mm3全封装植入式装置，具有双工超声数据和电源链路，在8.5cm深度下达到95kb/s, BER <10−4

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870460

T. Chang, Max L. Wang, Jayant Charthad, Marcus J. Weber, A. Arbabian

引用次数: 40

9.3 A BJT-based temperature sensor with a packaging-robust inaccuracy of ±0.3°C (3σ) from −55°C to +125°C after heater-assisted voltage calibration 9.3基于bjt的温度传感器，加热辅助电压校准后，在- 55°C至+125°C范围内，封装稳扎性误差为±0.3°C (3σ)

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870311

B. Yousefzadeh, K. Makinwa

引用次数: 19

24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS 24.4 A 0.18V 382µW蓝牙低功耗(BLE)接收器，1.33nW休眠功率，用于28nm CMOS的能量收集应用

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870437

Wei-Han Yu, Haidong Yi, Pui-in Mak, Jun Yin, R. Martins

引用次数: 29

21.2 A 1.4mΩ-sensitivity 94dB-dynamic-range electrical impedance tomography SoC and 48-channel Hub SoC for 3D lung ventilation monitoring system 21.2用于三维肺通气监测系统的1.4mΩ-sensitivity 94db动态范围电阻抗断层成像SoC和48通道Hub SoC

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870407

Minseo Kim, Hyunki Kim, Jaeeun Jang, Jihee Lee, Jaehyuk Lee, Jiwon Lee, Kyungrog Lee, Kwantae Kim, Yongsu Lee, H. Yoo

{"title":"21.2 A 1.4mΩ-sensitivity 94dB-dynamic-range electrical impedance tomography SoC and 48-channel Hub SoC for 3D lung ventilation monitoring system","authors":"Minseo Kim, Hyunki Kim, Jaeeun Jang, Jihee Lee, Jaehyuk Lee, Jiwon Lee, Kyungrog Lee, Kwantae Kim, Yongsu Lee, H. Yoo","doi":"10.1109/ISSCC.2017.7870407","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870407","url":null,"abstract":"Electrical impedance tomography (EIT) has been studied to monitor lung ventilation because it is the only real-time lung imaging method without large equipment [1–2]. However, previous EIT systems just provided 2D cross-sectional image with limited spatial information of the lung and unneglectable volume detection error depending on the location of 2D EIT belt relative to the patient's lung. In spite of its importance, the 3D-EIT has not been realized in lung monitoring because it has many design challenges such as noises incurred by complicated wiring, long cable length, wide variation in electrode contact and signal, and large personal-to-person impedance variation. In this paper, we present a portable 3D-EIT SoC for real-time lung ventilation monitoring with following 5 features: 1) The active electrodes (AEs) system to reduce coupling noise, 2) High output impedance current stimulator to inject stable current, 3) Impedance spectroscopy to enable both time-difference (TD) EIT and frequency-difference (FD) EIT, and to select an optimal frequency for TD-EIT, 4) Wide-dynamic range front-end circuit to detect variable ranges of signal with high-input impedance and CMRR, 5) Calibration to reduce the electrical characteristics variations of AEs.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133175460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory 11.4 512Gb 3b/cell 64堆叠WL 3D V-NAND闪存

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870331

Chulbum Kim, Ji-Ho Cho, Woopyo Jeong, I. Park, Hyun-wook Park, Doo-Hyun Kim, D. Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-Lo Ahn, Jiyoung Lee, Jonghoon Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jong-Yeol Park, Seunghwan Song, Yongha Park, Jinbae Bang, Sangki Hong, B. Jeong, Hyun-Jin Kim, Chunan Lee, Young-Sun Min, Inryul Lee, In-Mo Kim, Sung-Hoon Kim, Dongkyu Yoon, KiSeung Kim, Youngdon Choi, Moosung Kim, Hyunggon Kim, Pansuk Kwak, Jeong-Don Ihm, D. Byeon, Jin-Yub Lee, Ki-Tae Park, K. Kyung

{"title":"11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory","authors":"Chulbum Kim, Ji-Ho Cho, Woopyo Jeong, I. Park, Hyun-wook Park, Doo-Hyun Kim, D. Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-Lo Ahn, Jiyoung Lee, Jonghoon Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jong-Yeol Park, Seunghwan Song, Yongha Park, Jinbae Bang, Sangki Hong, B. Jeong, Hyun-Jin Kim, Chunan Lee, Young-Sun Min, Inryul Lee, In-Mo Kim, Sung-Hoon Kim, Dongkyu Yoon, KiSeung Kim, Youngdon Choi, Moosung Kim, Hyunggon Kim, Pansuk Kwak, Jeong-Don Ihm, D. Byeon, Jin-Yub Lee, Ki-Tae Park, K. Kyung","doi":"10.1109/ISSCC.2017.7870331","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870331","url":null,"abstract":"The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014 [1], the memory array size has nearly doubled every year [2,3]. To continue scaling 3D NAND array density, it is essential to scale down vertically to minimize total mold height. However, vertical scaling results in critical problems such as increasing WL capacitance and non-uniformity of stacked WLs due to variation in the channel hole diameter. To tackle these issues, this work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133183200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 59

4.1 A 640×480 dynamic vision sensor with a 9µm pixel and 300Meps address-event representation 4.1 640×480动态视觉传感器，9µm像素，300Meps地址事件表示

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870263

Bongki Son, Yunjae Suh, Sungho Kim, Heejae Jung, Jun-Seok Kim, Chang-Woo Shin, Keunju Park, Kyoobin Lee, Jin Man Park, J. Woo, Yohan J. Roh, Hyunku Lee, Y. Wang, I. Ovsiannikov, H. Ryu

{"title":"4.1 A 640×480 dynamic vision sensor with a 9µm pixel and 300Meps address-event representation","authors":"Bongki Son, Yunjae Suh, Sungho Kim, Heejae Jung, Jun-Seok Kim, Chang-Woo Shin, Keunju Park, Kyoobin Lee, Jin Man Park, J. Woo, Yohan J. Roh, Hyunku Lee, Y. Wang, I. Ovsiannikov, H. Ryu","doi":"10.1109/ISSCC.2017.7870263","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870263","url":null,"abstract":"We report a VGA dynamic vision sensor (DVS) with a 9µm pixel, developed through a digital as well as an analog implementation. DVS systems in the literature try to increase spatial resolution up to QVGA [1–2] and data rates up to 50 million events per second (Meps) (self-acknowledged) [3], but they are still inadequate for high-performance applications such as gesture recognition, drones, automotive, etc. Moreover, the smallest reported pixel of 18.5µm is too large for economical mass production [3]. This paper reports a 640×480 VGA-resolution DVS system with a 9µm pixel pitch supporting a data rate of 300Meps for sufficient event transfer in spite of higher resolution. Maintaining acceptable pixel performance, the pixel circuitry is carefully designed and optimized using a BSI CIS process. To acquire data (i.e., pixel events) at high speed even with high resolution (e.g., VGA), a fully synthesized word-serial group address-event representation (G-AER) is implemented, which handles massive events in parallel by binding neighboring 8 pixels into a group. In addition, a 10b programmable bias generator dedicated to a DVS system provides easy controllability of pixel biases and event thresholds.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127670110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 136

27.6 Single-chip 3072ch 2D array IC with RX analog and all-digital TX beamformer for 3D ultrasound imaging 27.6单片3072ch 2D阵列IC，带有RX模拟和全数字TX波束形成器，用于3D超声成像

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870459

Y. Katsube, Shinya Kajiyama, Takuma Nishimoto, T. Nakagawa, Yasuyuki Okuma, Yohei Nakamura, T. Terada, Yutaka Igarashi, T. Yamawaki, T. Yazaki, Y. Hayashi, Kazuhiro Amino, Takuya Kaneko, Hiroki Tanaka

引用次数: 14