29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS

Abstract

Asymmetric links such as memory interfaces and display drivers require the transmitter to perform necessary equalization, while the receiver remains simple and has minimal or no equalization capability. Traditionally, FFE-based equalization techniques on power-efficient voltage-mode drivers have been used on the transmit end. Based on the FFE tap resolution requirement, the output driver and pre-driver are divided into multiple segments. Although such a segmented FFE implementation helps to maintain a constant output termination impedance (50Ω) across all tap settings, it comes at the cost of (a) increased signaling power, and (b) increased switching power since multiple segments are required to achieve desired linearity [1]. Phase domain equalization techniques, such as pulse width modulation (PWM), can equalize the channel without increasing signaling power or segmenting the output driver. However, PWM encoding requires the insertion of a precise narrow pulse in every data bit, which necessitates very wide bandwidth in the high-speed data path, resulting in poor energy efficiency [2] and difficulty in scaling PWM encoding to higher data rates [3]. For example, creating a 10% duty cycle on a 64Gb/s PWM data stream would require a pulse width of 1.5ps with less than 1ps of rise/fall time at the transmitter output. Other phase domain pre-emphasis techniques are ineffective for high-loss channels [4]. In view of these limitations, we present a new phase-domain equalization technique: integrated pulse width modulation (iPWM) in a 16Gb/s transceiver, which can equalize 19dB of channel loss, while consuming 57.3mW power. Compared to state-of-the-art PWM designs, the proposed iPWM scheme achieves 36× better energy efficiency for the same data rate [2], and 3.2× higher data rate for the same energy efficiency [3].