2017 IEEE International Solid-State Circuits Conference (ISSCC)最新文献_第7页

20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS 20.5一种用于28nm CMOS应用处理器的具有动态动力电池和最小化交叉调节的双对称输出开关电容变换器

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870402

Junmin Jiang, Yan Lu, W. Ki, U. Seng-Pan, R. Martins

{"title":"20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS","authors":"Junmin Jiang, Yan Lu, W. Ki, U. Seng-Pan, R. Martins","doi":"10.1109/ISSCC.2017.7870402","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870402","url":null,"abstract":"Multicore application processors in smartphones/watches use power-saving techniques such as dynamic voltage and frequency scaling (DVFS) to extend battery cycle, and supply cores with different voltages [1]. High-efficiency fully integrated switched-capacitor (SC) power converters with no external components are promising candidates [2]. Typically, SC converters with different specifications are independently designed (Fig. 20.5.1), leading to a large area overhead, as each converter has to handle its peak output power. Recently, multi-output SC converters are reported to tackle this issue. In [3], an on-demand strategy is used to control two outputs, each with a different loading range, and the outputs are not interchangeable. In [4], the two output voltages are fixed with voltage conversion ratios (VCRs) of 2× and 3× only. In [5], the controller is integrated, but the three output voltages are still from three individual SC converters. Without reallocating the capacitors in the power stages, capacitor utilization is low, as margins have to be reserved to cater for each converter's peak output power. This paper presents a fully integrated dual-output SC converter with dynamic power-cell allocation for application processors. The power cells are shared and can be dynamically allocated according to load demands. A dual-path VCO that works independently of power-cell allocation is proposed to realize a fast and stable regulation loop. The converter can deliver a maximum current of 100mA: one output can be adjusted to deliver 100mA, while the other handles a very light load; or both outputs can be adjusted to deliver 50mA each with over 80% efficiency.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123494897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET 28.5 A 10b 1.5GS/s流水线sar ADC，具有背景第二级共模调节和14nm CMOS FinFET的失调校准

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870467

L. Kull, D. Luu, C. Menolfi, M. Braendli, P. Francese, T. Morf, M. Kossel, Hazar Yueksel, A. Cevrero, Ilter Özkaya, T. Toifl

{"title":"28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET","authors":"L. Kull, D. Luu, C. Menolfi, M. Braendli, P. Francese, T. Morf, M. Kossel, Hazar Yueksel, A. Cevrero, Ilter Özkaya, T. Toifl","doi":"10.1109/ISSCC.2017.7870467","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870467","url":null,"abstract":"High-speed SAR ADCs became popular with modern CMOS technologies because of their mostly digital logic, making them highly suitable for compact and power-efficient multi-GS/s time-interleaved ADCs. As many applications cannot tolerate input swings ≥1Vppd, comparator noise limits the SNDR of SAR ADCs, making gain stages necessary for higher SNDR - either as comparator pre-amplifiers or between pipelined stages. Pre-amplifiers significantly reduce the conversion speed of the ADC, but they provide maximum SNDR because linearity of the amplifier is irrelevant. An interstage amplifier for pipelining best suits mid-resolution SAR ADCs, where the required linearity is limited. Moreover, pipelining results in higher conversion speeds and power efficiency because the gain stage is used only once per conversion [1]. This work presents a pipelined-SAR ADC architecture that exceeds the conversion speed of previous pipelined and single-stage SAR ADCs. The ADC achieves 50dB SNDR and 950MS/s at 2.26mW, and 1.5GS/s at 6.92mW on an area of 0.0016mm2.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124867820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 56

F4: Wireless low-power transceivers for local and wide-area networks F4:用于局域网和广域网的无线低功耗收发器

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870482

J. V. Sinderen, D. Griffith, Ken Yamamoto, A. Liscidini, Young-sub Yuk

引用次数: 0

2.2 A fully integrated reconfigurable wideband envelope-tracking SoC for high-bandwidth WLAN applications in a 28nm CMOS technology 2.2完全集成的可重构宽带包络跟踪SoC，适用于28nm CMOS技术的高带宽WLAN应用

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870247

D. Chowdhury, Sraavan R. Mundlapudi, A. Afsahi

引用次数: 14

20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS 20.1采用14nm三栅极CMOS工艺，采用平面磁芯的片上螺线管电感式全集成数字控制稳压器

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870398

H. Krishnamurthy, V. Vaidya, Sheldon Weng, K. Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, G. Matthew, J. Tschanz, V. De

引用次数: 17

27.5 A pixel-pitch-matched ultrasound receiver for 3D photoacoustic imaging with integrated delta-sigma beamformer in 28nm UTBB FDSOI 27.5 28nm UTBB FDSOI集成delta-sigma波束形成器用于三维光声成像的像素-间距匹配超声接收器

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870458

Man-Chia Chen, A. Perez, Sri-Rajasekhar Kothapalli, P. Cathelin, A. Cathelin, S. Gambhir, B. Murmann

引用次数: 16

21.1 Nanowatt circuit interface to whole-cell bacterial sensors 21.1纳瓦电路接口到全细胞细菌传感器

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870406

P. Nadeau, M. Mimee, Sean Carim, T. Lu, A. Chandrakasan

引用次数: 18

12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50% 12.4 1.4Gsearch/s 2Mb/mm2 TCAM采用两相预充ML传感和电网预处理，将Ldi/dt电源噪声降低50%

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870336

I. Arsovski, Michael Fragano, R. Houle, A. Patil, V. Butler, Raymond Kim, R. Rodriguez, T. Maffitt, J. J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, S. Burns

引用次数: 3

9.8 An energy-efficient 3.7nV/√Hz bridge-readout IC with a stable bridge offset compensation scheme 9.8具有稳定电桥偏置补偿方案的3.7nV/√Hz高能效电桥读出IC

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870316

Hui Jiang, K. Makinwa, S. Nihtianov

引用次数: 31

29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS 29.4 A 16Gb/s 3.6pJ/b有线收发器，相位域均衡方案:65nm CMOS集成脉宽调制(iPWM)

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870474

Ashwin Ramachandran, A. Natarajan, Tejasvi Anand

{"title":"29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS","authors":"Ashwin Ramachandran, A. Natarajan, Tejasvi Anand","doi":"10.1109/ISSCC.2017.7870474","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870474","url":null,"abstract":"Asymmetric links such as memory interfaces and display drivers require the transmitter to perform necessary equalization, while the receiver remains simple and has minimal or no equalization capability. Traditionally, FFE-based equalization techniques on power-efficient voltage-mode drivers have been used on the transmit end. Based on the FFE tap resolution requirement, the output driver and pre-driver are divided into multiple segments. Although such a segmented FFE implementation helps to maintain a constant output termination impedance (50Ω) across all tap settings, it comes at the cost of (a) increased signaling power, and (b) increased switching power since multiple segments are required to achieve desired linearity [1]. Phase domain equalization techniques, such as pulse width modulation (PWM), can equalize the channel without increasing signaling power or segmenting the output driver. However, PWM encoding requires the insertion of a precise narrow pulse in every data bit, which necessitates very wide bandwidth in the high-speed data path, resulting in poor energy efficiency [2] and difficulty in scaling PWM encoding to higher data rates [3]. For example, creating a 10% duty cycle on a 64Gb/s PWM data stream would require a pulse width of 1.5ps with less than 1ps of rise/fall time at the transmitter output. Other phase domain pre-emphasis techniques are ineffective for high-loss channels [4]. In view of these limitations, we present a new phase-domain equalization technique: integrated pulse width modulation (iPWM) in a 16Gb/s transceiver, which can equalize 19dB of channel loss, while consuming 57.3mW power. Compared to state-of-the-art PWM designs, the proposed iPWM scheme achieves 36× better energy efficiency for the same data rate [2], and 3.2× higher data rate for the same energy efficiency [3].","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130538558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9