20.1采用14nm三栅极CMOS工艺，采用平面磁芯的片上螺线管电感式全集成数字控制稳压器

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-01 DOI:10.1109/ISSCC.2017.7870398

H. Krishnamurthy, V. Vaidya, Sheldon Weng, K. Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, G. Matthew, J. Tschanz, V. De

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引用次数: 17

摘要

完全集成的片上降压稳压器(VR)为复杂soc中高功率密度的细颗粒DVFS域提供了高效、宽范围的局部供电和管理能力，并具有快速的瞬态响应。集成高质量的功率电感器，以最小的损耗支持高电流密度是一个主要的挑战。

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20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS

Fully integrated on-die buck voltage regulators (VR) promise efficient and wide-range local power delivery and management capability with fast transient response for fine-grain DVFS domains of high power density in complex SoCs. Integration of high-quality power inductors that can support high current density with minimal losses is a major challenge.

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2017 IEEE International Solid-State Circuits Conference (ISSCC)

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