2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)最新文献

Fractal Shape Dual-Band EBG integrated Textile Antenna 分形双频EBG集成纺织天线

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2019-05-01 DOI: 10.1109/RTEICT46194.2019.9016931

Snehal Kapse, S. B. Gundre

引用次数: 1

Implementation of fuzzy logic control for FOPDT model of distillation column 精馏塔FOPDT模型的模糊逻辑控制实现

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2019-05-01 DOI: 10.1109/RTEICT46194.2019.9016877

Samruddhi Chavan, Vivek Rathi, Namrata Birnale

引用次数: 5

Design of 8 Bit Vedic Multiplier Using Urdhva Tiryagbhyam Sutra With Modified Carry Save Adder 基于Urdhva Tiryagbhyam经的8位吠陀乘法器设计与改进进位保存加法器

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2019-05-01 DOI: 10.1109/RTEICT46194.2019.9016965

M. Chandrashekara, S. Rohith

{"title":"Design of 8 Bit Vedic Multiplier Using Urdhva Tiryagbhyam Sutra With Modified Carry Save Adder","authors":"M. Chandrashekara, S. Rohith","doi":"10.1109/RTEICT46194.2019.9016965","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016965","url":null,"abstract":"This paper mainly describes the design of 8-bit Vedic multiplier and its performance comparison with existing multiplier such as i) Booth multiplier ii) Array multiplier iii) Wallace tree multiplier. Vedic calculations are the olden scheme of mathematics, which has a procedure of mathematical calculations to compute the multiplication of two 8-bit number. In this work Urdhva Tiryagbhyam (vertical and crosswise) Vedic sutra is used for multiplier design which provides better performance and consumes lesser time for computation. The Urdhva Tiryagbhyam is the finest sutra and universal one among additional sutras and which represents the different multiplication process compared to normal multiplication. In this work, Modified Carry Save Adder (MCSA) is used to compute the sum of partially generated products. It reduces the computational delay towards the addition of unfinished products. The proposed design uses the Verilog HDL to develop the algorithm. The XILINX 14.7 software tool is used to simulate and synthesize the code. The proposed design is also verified on Spartan-6 Field Programmable Gate Array (FPAGA). Finally, the proposed 8-bit multiplier design is compared with 8-bit Booth multiplier, Array multiplier and Wallace tree multiplier in terms of Area, Memory and Delay. The result shows proposed 8-bit Vedic multiplier is efficient and consumes 14.219ns time for the multiplication process which is better compared to 8-bit, Booth multiplier, Array multiplier and Wallace tree multiplier.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125403916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Simulation and Evaluation of Different Mobility Models in Disaster Scenarios 灾害情景下不同机动模式的仿真与评估

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2019-05-01 DOI: 10.1109/RTEICT46194.2019.9016893

G. Walunjkar, A. Koteswara Rao

引用次数: 6

Fast BIST Mechanism for Faster Validation of Memory Array 存储器阵列快速验证的快速BIST机制

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2019-05-01 DOI: 10.1109/RTEICT46194.2019.9016882

Shrinidhi N Bagewadi, Syed Shadab, J. Roopa

{"title":"Fast BIST Mechanism for Faster Validation of Memory Array","authors":"Shrinidhi N Bagewadi, Syed Shadab, J. Roopa","doi":"10.1109/RTEICT46194.2019.9016882","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016882","url":null,"abstract":"Memories constitute a major portion of any system on chip(SoC). As the density in the SoC is increasing, the requirement on increased size of memories present also increasing. Testing of such large memories becomes an increasingly challenging task. Memory Built-in self-test (MBIST) is a built in self-test used for memories conventionally, which is used to verify the functionality of the memory and detect faults in the memory arrays. With the pace of growing technology, time to market plays an important role for any product and thus this leads to demand for optimizing MBIST mechanism for faster validation of memories. Increasing the frequency of operation is not an option as it might disturb signatures in the memory. Also, due to large amount of memory present, it becomes time consuming to test every bit of memory on SoC. In this paper, it is shown to reduce the test time for the memories at pre-silicon stage. Thus, a novel Fast BIST mechanism is proposed that uses selective testing of memories in the array which uses sampling method for testing the memories. Using this mechanism reduces testing time significantly. Thus this can be used in pre-silicon stages of SoC as well as for tests that may not require full memory scan. When Fast BIST is implemented on a memory array of 32x4096 for 50% of addresses at 500MHz test frequency, we can achieve as high as 31.01% reduction in testing time by running tests over limited addresses. Similarly we can achieve 56% improvement for 10% addresses.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130555104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Artificial Neural Network based Automatic Speech Recognition Engine for Voice Controlled Micro Air Vehicles 基于人工神经网络的声控微型飞行器语音识别引擎

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2019-05-01 DOI: 10.1109/RTEICT46194.2019.9016983

Sushma. M. Gowda, D. K. Rahul, A. Anand, S. Veena, V. B. Durdi

引用次数: 1

Recognition and Prediction of Breast Cancer using Supervised Diagnosis 使用监督诊断识别和预测乳腺癌

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2019-05-01 DOI: 10.1109/RTEICT46194.2019.9016921

Harshitha, V. Chaitanya, Shazia M Killedar, Dheeraj Revankar, M. Pushpa

{"title":"Recognition and Prediction of Breast Cancer using Supervised Diagnosis","authors":"Harshitha, V. Chaitanya, Shazia M Killedar, Dheeraj Revankar, M. Pushpa","doi":"10.1109/RTEICT46194.2019.9016921","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016921","url":null,"abstract":"Breast cancer is the most common and a major death causing disease diagnosed among women worldwide. Early detection of this disease can reduce the death rates. Image processing techniques using machine learning are widely used in medical domain to improve the early detection of cancerous tumors in breast. In this proposed approach, supervised learning techniques are used to extract cancer defining features and classify cancerous images from the normal mammogram images. The supervised system is initially trained by extracting 13 features each from a dataset of 30 images. The extracted features of the image under test are associated with the features extracted from the database images to detect and predict the cancer tumor in the image. Support Vector Machine (SVM) and K-Nearest Neighbours(KNN) is used for classification. Based on the analysis, the system is capable to give a classification accuracy of 95%(SVM) and 97% (KNN). A GUI based interface is also developed for the same. Further, a user-friendly chatbot is developed using Dialog Flow, which interacts with patients to predict cancer based on the symptoms identified by the patient. This chatbot can be used by the patient to detect whether the symptoms are porne to cancer.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125612525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Design and Implementation of Low Power - High Performance Mixed Logic Line Decoders 低功耗-高性能混合逻辑线解码器的设计与实现

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2019-05-01 DOI: 10.1109/RTEICT46194.2019.9016923

N. S. Sumana, B. Sahana, Abhay Deshapande

{"title":"Design and Implementation of Low Power - High Performance Mixed Logic Line Decoders","authors":"N. S. Sumana, B. Sahana, Abhay Deshapande","doi":"10.1109/RTEICT46194.2019.9016923","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016923","url":null,"abstract":"This paper proposes a mixed logic design technique for implementation of low power - high speed line decoders. Mixed logic design method combines Pass transistor- Dual Value Logic (DVL), Transmission Gate Logic(TGL) and Static CMOS logic. 2–4 decoders are implemented using two novel topologies, a 14-transistor low power topology for reducing power and a 15-transistor high performance topology for minimizing delay and power dissipation with reduced number of transistors in each case. In each case both non-inverting and inverting decoders are implemented, thus providing a total of four new decoder designs. 4–16 decoders are implemented using 2–4 mixed logic pre-decoders and CMOS post-decoder. Mixed logic decoders provide full-swung capability. Furthermore, all the proposed 2–4 decoders are implemented with enable input, this design eliminates the CMOS post decoder and provides a complete mixed logic 4–16 decoder. All the proposed decoders are implemented using Cadence Virtuoso tool in 180nm technology and the simulation results prove that the mixed logic decoders provide a significant improvement in power and delay with reduced number of transistors, outperforming conventional CMOS decoders in almost all cases.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125997018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Handover Mechanism in 5G mmwave Band 5G毫米波频段的切换机制

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2019-05-01 DOI: 10.1109/RTEICT46194.2019.9016943

G. Spoorthi, M. B. Akkamahadevi

引用次数: 2

Design of a Delta Threshold Voltage Difference based fully Embedded Read Only Memory along with a Skew Sense Amplifier 基于δ阈值电压差的全嵌入式只读存储器和倾斜感测放大器的设计

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2019-05-01 DOI: 10.1109/RTEICT46194.2019.9016855

V. Balaji, Ch.K.S.D. Ranga, N. Shylashree, N. Praveena

{"title":"Design of a Delta Threshold Voltage Difference based fully Embedded Read Only Memory along with a Skew Sense Amplifier","authors":"V. Balaji, Ch.K.S.D. Ranga, N. Shylashree, N. Praveena","doi":"10.1109/RTEICT46194.2019.9016855","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016855","url":null,"abstract":"This paper describes the design and implementation of an embedded ROM memory along with its sense amplifier. Several applications in machine learning have fixed data to be stored in a memory, which needs to be read out multiple times. Hence a fast, on-chip solution is proposed in this technical paper wherein logic transistors are used to design a read only memory with completely zero added process complexity. Several design constraints of sensing the ROM cell have been elaborated to a great extent. Also, a key advantage in the sense amplifier used is the ability to use all transistors from the same process technology. Further, by always fixing a MOS device in saturation and the other MOS device in cut off region, fast sensing is achieved at the sense amplifier output. The layout designed for the sense amplifier is verified to produce a very minimal deviation from the actual schematic simulations, hence suggesting a considerably well designed layout. The operating frequency of the sense amplifier is determined as 12.5 GHz with full swing resolution.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133887748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0