Design and Implementation of Low Power - High Performance Mixed Logic Line Decoders

This paper proposes a mixed logic design technique for implementation of low power - high speed line decoders. Mixed logic design method combines Pass transistor- Dual Value Logic (DVL), Transmission Gate Logic(TGL) and Static CMOS logic. 2–4 decoders are implemented using two novel topologies, a 14-transistor low power topology for reducing power and a 15-transistor high performance topology for minimizing delay and power dissipation with reduced number of transistors in each case. In each case both non-inverting and inverting decoders are implemented, thus providing a total of four new decoder designs. 4–16 decoders are implemented using 2–4 mixed logic pre-decoders and CMOS post-decoder. Mixed logic decoders provide full-swung capability. Furthermore, all the proposed 2–4 decoders are implemented with enable input, this design eliminates the CMOS post decoder and provides a complete mixed logic 4–16 decoder. All the proposed decoders are implemented using Cadence Virtuoso tool in 180nm technology and the simulation results prove that the mixed logic decoders provide a significant improvement in power and delay with reduced number of transistors, outperforming conventional CMOS decoders in almost all cases.