Fast BIST Mechanism for Faster Validation of Memory Array

Abstract

Memories constitute a major portion of any system on chip(SoC). As the density in the SoC is increasing, the requirement on increased size of memories present also increasing. Testing of such large memories becomes an increasingly challenging task. Memory Built-in self-test (MBIST) is a built in self-test used for memories conventionally, which is used to verify the functionality of the memory and detect faults in the memory arrays. With the pace of growing technology, time to market plays an important role for any product and thus this leads to demand for optimizing MBIST mechanism for faster validation of memories. Increasing the frequency of operation is not an option as it might disturb signatures in the memory. Also, due to large amount of memory present, it becomes time consuming to test every bit of memory on SoC. In this paper, it is shown to reduce the test time for the memories at pre-silicon stage. Thus, a novel Fast BIST mechanism is proposed that uses selective testing of memories in the array which uses sampling method for testing the memories. Using this mechanism reduces testing time significantly. Thus this can be used in pre-silicon stages of SoC as well as for tests that may not require full memory scan. When Fast BIST is implemented on a memory array of 32x4096 for 50% of addresses at 500MHz test frequency, we can achieve as high as 31.01% reduction in testing time by running tests over limited addresses. Similarly we can achieve 56% improvement for 10% addresses.