Design of 8 Bit Vedic Multiplier Using Urdhva Tiryagbhyam Sutra With Modified Carry Save Adder

Abstract

This paper mainly describes the design of 8-bit Vedic multiplier and its performance comparison with existing multiplier such as i) Booth multiplier ii) Array multiplier iii) Wallace tree multiplier. Vedic calculations are the olden scheme of mathematics, which has a procedure of mathematical calculations to compute the multiplication of two 8-bit number. In this work Urdhva Tiryagbhyam (vertical and crosswise) Vedic sutra is used for multiplier design which provides better performance and consumes lesser time for computation. The Urdhva Tiryagbhyam is the finest sutra and universal one among additional sutras and which represents the different multiplication process compared to normal multiplication. In this work, Modified Carry Save Adder (MCSA) is used to compute the sum of partially generated products. It reduces the computational delay towards the addition of unfinished products. The proposed design uses the Verilog HDL to develop the algorithm. The XILINX 14.7 software tool is used to simulate and synthesize the code. The proposed design is also verified on Spartan-6 Field Programmable Gate Array (FPAGA). Finally, the proposed 8-bit multiplier design is compared with 8-bit Booth multiplier, Array multiplier and Wallace tree multiplier in terms of Area, Memory and Delay. The result shows proposed 8-bit Vedic multiplier is efficient and consumes 14.219ns time for the multiplication process which is better compared to 8-bit, Booth multiplier, Array multiplier and Wallace tree multiplier.