{"title":"Bifurcation diagrams in MOS-NDR frequency divider circuits","authors":"J. Núñez, M. Avedillo, J. Quintana","doi":"10.1109/ICECS.2012.6463558","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463558","url":null,"abstract":"The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an I-V characteristic exhibiting Negative Differential Resistance (NDR) built from MOS transistors plus an inductor and a resistor. Frequency division is obtained from the period adding sequences which appear in its bifurcation diagram. The analyzed circuit is an “all MOS” version of one previously reported which uses Resonant Tunneling Diodes (RTDs). The results show that the dividing ratio can be selected by modulating the input signal frequency, in a similar way to the RTD-based circuit.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133059596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hassan Abbass, Hawraa Amhaz, G. Sicard, David Alleysson
{"title":"In Pixel Implementation of autoadaptative integration time","authors":"Hassan Abbass, Hawraa Amhaz, G. Sicard, David Alleysson","doi":"10.1109/ICECS.2012.6463567","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463567","url":null,"abstract":"New auto-adaptative technique for linear CMOS image sensor based on double captures is presented in this paper. This technique permits to cover up to 6 order of luminosities magnitude. The different blocks composing the adaptative loop are developed in the CMOS 0.35μm technology from Austria MicroSystems. The emulation results of the MATLAB model are shown as well as the electrical simulations of the different blocks.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128419513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Zhang, F. Morel, C. Hu-Guo, A. Himmi, A. Dorokhov, Yann Hu
{"title":"A CMOS pixel sensor with 4-bit column-parallel self-triggered ADC for the ILC vertex detector","authors":"L. Zhang, F. Morel, C. Hu-Guo, A. Himmi, A. Dorokhov, Yann Hu","doi":"10.1109/ICECS.2012.6463509","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463509","url":null,"abstract":"This paper presents a CMOS Pixel Sensor (CPS) prototype for the outer layers of the future International Linear Collider (ILC) vertex detector. It is composed of a matrix of 48 × 64 pixels with a 4-bit column-parallel analog-to-digital converter (ADC). The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector the hit density is in the order of a few per thousand, this ADC works in two modes: active mode and inactive mode. The average energy and total capacitance are significantly reduced by a power-gating control and a switching network, respectively. The prototype sensor was fabricated in a 0.35 μm CMOS process with a pixel pitch of 35 μm. The designed 4-bit ADC dissipates, at a 3-V supply and 6.25-MS/s sampling rate, 486 μW in its inactive mode, which is by far the most frequent. This value rises to 714 μW in case of the active mode. Its footprint amounts to 35 × 545 μm2.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133919627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pargles Dall'Oglio, Cassio Cristani, M. Porto, L. Agostini
{"title":"A high quality hardware friendly motion estimation algorithm focusing in HD videos","authors":"Pargles Dall'Oglio, Cassio Cristani, M. Porto, L. Agostini","doi":"10.1109/ICECS.2012.6463682","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463682","url":null,"abstract":"Fast algorithms for motion estimation are often trapped in local minima, especially when working on high definition videos (HD). This paper presents a new algorithm for motion estimation focused on high definition videos named Multiple Iterative Random Search (MIRS). This algorithm uses randomness and multiple iterative steps as strategy to avoid local minima falls, achieving better quality results than traditional fast algorithms. MIRS is a hardware friendly algorithm since it has five iterative steps which did not have data dependencies, then these five iterative steps can be implemented in parallel, reaching a processing rate similar to other fast algorithms. That characteristic becomes MIRS a very competitive option for hardware implementation, since it is possible to reach very high processing rates with very good quality results. The comparative results show that MIRS algorithm presented the best PSNR among all evaluated fast algorithms. MIRS is also able to reduce in 70 times the number of evaluated blocks when compared with Full Search algorithm with a PSNR drop of only 0.71dB.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134274118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jidan Al-Eryani, Alexander Stanitzki, Karsten Konrad, Nima Tavangaran, D. Brückmann, R. Kokozinski
{"title":"Low-power area-efficient delay element with a wide delay range","authors":"Jidan Al-Eryani, Alexander Stanitzki, Karsten Konrad, Nima Tavangaran, D. Brückmann, R. Kokozinski","doi":"10.1109/ICECS.2012.6463625","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463625","url":null,"abstract":"A low-power, area-efficient delay element with a wide tunable delay range is proposed. A novel circuit topology is used, where the delay is set using a single control-voltage that controls both the charging and discharging time of a capacitor. A positive feedback mechanism minimizes and keeps the energy consumption constant for a wide delay range. Figure of merits are presented and comparison with previous works illustrates the improvements obtained.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133407481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Naser Khosro Pour, S. Facchin, F. Krummenacher, M. Kayal
{"title":"An ultra-low power li-ion battery charger for micro-power solar energy harvesting applications","authors":"Naser Khosro Pour, S. Facchin, F. Krummenacher, M. Kayal","doi":"10.1109/ICECS.2012.6463695","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463695","url":null,"abstract":"This paper presents an ultra-low power, fully integrated solar energy harvester circuit for autonomous microsystems. The proposed circuit harvests solar energy from a micro-power photovoltaic module and stores the harvested energy in a miniaturized thin film Li-Ion microbattery, using a highly area- and power-efficient power management circuit. As neither inductor, nor large pumping capacitors have been used in this circuit, it occupies less area comparing to conventional inductive and switched-capacitor DC-DC converters. In addition, thanks to low power design of this circuit, it achieves more than 94% efficiency during battery charging. Even under reduced light intensity, when the harvested energy is only a few tens of microwatts, more than 92% efficiency is achievable. The proposed microsystem has been implemented in a 0.18μm CMOS process and occupies a core area of only 0.12mm2. This circuit features a low power consumption of 270nW in average.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126968089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Understanding large swing and low swing operation in DyCML gates","authors":"Tiago Borges, E. Martins, L. N. Alves","doi":"10.1109/ICECS.2012.6463675","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463675","url":null,"abstract":"This paper investigates the operation of dynamic current-mode logic gates (DyCML), under large swing and low swing conditions. Traditionally, the operation of DyCML gates is ruled by charge distribution models, stating that, the output charge is transferred during the evaluation phase to a dynamic current source capacitor. Output swing is governed by the ratio between load and dynamic source capacitances, which are able to accommodate all the output voltage swing. This paper shows that this model is not adequate for all output swing conditions; in particular there are two different modes that need to be considered. Simulation results, using a standard 350nm CMOS process provide evidence of these different behaviors. Second order effects are also considered, providing guidelines for future research.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124670399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kaushik Ghosal, Tejasvi Anand, V. Chaturvedi, B. Amrutur
{"title":"A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applications","authors":"Kaushik Ghosal, Tejasvi Anand, V. Chaturvedi, B. Amrutur","doi":"10.1109/ICECS.2012.6463775","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463775","url":null,"abstract":"A power scalable receiver architecture is presented for low data rate Wireless Sensor Network (WSN) applications in 130nm RF-CMOS technology. Power scalable receiver is motivated by the ability to leverage lower run-time performance requirement to save power. The proposed receiver is able to switch power settings based on available signal and interference levels while maintaining requisite BER. The Low-IF receiver consists of Variable Noise and Linearity LNA, IQ Mixers, VGA, Variable Order Complex Bandpass Filter and Variable Gain and Bandwidth Amplifier (VGBWA) capable of driving variable sampling rate ADC. Various blocks have independent power scaling controls depending on their noise, gain and interference rejection (IR) requirements. The receiver is designed for constant envelope QPSK-type modulation with 2.4GHz RF input, 3MHz IF and 2MHz bandwidth. The chip operates at 1V Vdd with current scalable from 4.5mA to 1.3mA and chip area of 0.65mm2.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"657 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127543276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A low-distortion switched-source-follower track-and-hold circuit","authors":"Akinori Moriyama, S. Taniyama, T. Waho","doi":"10.1109/ICECS.2012.6463788","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463788","url":null,"abstract":"A novel switched-source-follower track-and-hold (T/H) circuit has been proposed, where an input source-coupled pair conventionally used preceding the source-follower switch is replaced with another source-follower stage. Suppressing signal-dependent sample-timing jitter, which is due to the channel-length modulation of the input transistor, leads to a low-distortion T/H operation. Circuit simulation assuming a 0.1-μm InP-based HEMT technology has revealed an SFDR improvement from 58dB to 70dB for input and sampling frequencies of 3 GHz and 20 GHz, respectively. Although the present result is based on the high-speed compound semiconductor technology, the idea behind this can be applied to T/H circuits using nano-scale MOSFETs with reduced output impedance.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129039345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient area and power multiplication part of FFT based on twiddle factor decomposition","authors":"S. Ghissoni, E. Costa, J. Monteiro, R. Reis","doi":"10.1109/ICECS.2012.6463640","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463640","url":null,"abstract":"This paper presents an efficient area and power multiplication part of radix-2 FFT (Fast Fourier Transform) architecture. The butterfly plays a central role in the FFT computation, and the multiplication part dominates its complexity. It is composed by a product of complex data and complex coefficients named twiddle factors. The proposed strategy consists on the decomposition of the real and imaginary coefficients of the twiddle factors into less complex ones, so that the multiplication part of the butterfly can be implemented with less area, what leads to the reduction of its power consumption. The strategy also includes the use of Constant Matrix Multiplication (CMM) and gate level approaches in the decomposed coefficients. A control unit is responsible for selecting the correct constant to be used after the decomposition. The proposed architectures were synthesized using SYNOPSYS Design Compiler and the UMC130nm technology. The results show that reductions of 10% in area and 8% in power could be achieved on average, when compared with state of the art solutions.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127766345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}