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2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)最新文献

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Accurate estimation of analog test metrics with extreme circuits 精确估计模拟测试指标与极端电路
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-09 DOI: 10.1109/ICECS.2012.6463748
Kamel Beznia, A. Bounceur, L. Abdallah, K. Huang, S. Mir, R. Euler
{"title":"Accurate estimation of analog test metrics with extreme circuits","authors":"Kamel Beznia, A. Bounceur, L. Abdallah, K. Huang, S. Mir, R. Euler","doi":"10.1109/ICECS.2012.6463748","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463748","url":null,"abstract":"Specification-based testing of analog/RF circuits is very costly due to lengthy test times and highly sophisticated test equipment. Alternative test measures, extracted by means of Built-In Test (BIT) techniques, are a promising approach to replace standard specification-based tests. However, these test measures must be evaluated at the design stage, before the real production, by estimating parametric test errors such as Test Escapes (TE) and Yield Loss (YL). An accurate estimation of these metrics requires a large non-biased sample of circuit instances including parametric defective ones. Since these extreme circuits are rare events, they cannot be obtained with a Monte Carlo simulation of an affordable size. However, statistical learning techniques, in combination with Monte Carlo simulation, can allow the generation of such a sample for multivariate test metrics estimation. In this paper, we will demonstrate this technique for the evaluation of an RF LNA BIT technique for which a large database of 106 circuits has been simulated for comparison purposes.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121373423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A multi-valued 350nm CMOS voltage reference 多值350nm CMOS电压基准
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463668
Nuno Lourenço, L. N. Alves, J. L. Cura
{"title":"A multi-valued 350nm CMOS voltage reference","authors":"Nuno Lourenço, L. N. Alves, J. L. Cura","doi":"10.1109/ICECS.2012.6463668","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463668","url":null,"abstract":"This paper describes, a voltage reference source using sub-threshold MOSFETs. The circuit supports supply voltages ranging from 1.5V to 3.3V and temperature variations ranging from -20°C to 80°C. Different values for the voltage reference can be achieved without severe performance impairments. The proposed circuit was produced in the 350nm CMOS process from AMS and occupies less than 0.0335mm2. Simulation and experimental data show that this circuit is able to achieve, a 3mV variation for the entire temperature span and a 2mV variation for the entire supply voltage span.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115415792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ultra-low voltage drain-bulk connected MOS transistors in weak and moderate inversion 弱和中等反转的超低电压漏极体连接MOS晶体管
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463711
Athanasios Dimakos, M. Bucher, R. K. Sharma, Ilias Chlis
{"title":"Ultra-low voltage drain-bulk connected MOS transistors in weak and moderate inversion","authors":"Athanasios Dimakos, M. Bucher, R. K. Sharma, Ilias Chlis","doi":"10.1109/ICECS.2012.6463711","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463711","url":null,"abstract":"This paper aims to demonstrate the basic characteristics of NMOS and PMOS drain-bulk connected transistors for ultra-low voltage applications. On-wafer measurements were done on 180nm CMOS process, while TCAD simulations were done for 180nm and 45nm technology nodes. Analytical expressions for Early voltage and intrinsic gain in weak-moderate inversion are provided, showing that these quantities are dominated by the substrate effect and are insensitive to bias and geometry. Furthermore, the analytical model as well as the EKV3 MOSFET compact model, following suitable parameter extraction, show a close agreement to measured and TCAD simulated data.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115704440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An RTL method for hiding clock domain crossing latency 一种隐藏时钟域交叉延迟的RTL方法
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463557
Ghaith Tarawneh, A. Yakovlev
{"title":"An RTL method for hiding clock domain crossing latency","authors":"Ghaith Tarawneh, A. Yakovlev","doi":"10.1109/ICECS.2012.6463557","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463557","url":null,"abstract":"We present an architectural method to hide the latency incurred by synchronization when transferring data between clock domains. Unlike existing solutions, ours does not rely on any timing assumptions between the communicating clocks and is transparent to the design. We demonstrate how to apply the proposed method to a generic Moore machine with an asynchronous port and then describe how this process can be automated by a Register Transfer Level tool. Using an implementation of the tool, we apply our method to six communication controllers and show that it incurs, on average, only 8% of the area of a periodic synchronizer.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125566539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Layout stress and proximity aware analog design methodology 布局应力和接近感知模拟设计方法
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463667
A. Zein, Amr Tarek, Mohamed Bahr, M. Dessouky, H. Eissa, A. Ramadan, Amr M. S. Tosson
{"title":"Layout stress and proximity aware analog design methodology","authors":"A. Zein, Amr Tarek, Mohamed Bahr, M. Dessouky, H. Eissa, A. Ramadan, Amr M. S. Tosson","doi":"10.1109/ICECS.2012.6463667","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463667","url":null,"abstract":"This paper presents a new methodology for analog circuits design which takes into account layout dependent effects and layout interdependencies between devices. Analog Devices' performance is impacted by other layout features located in near context. These layout effects can lead to catastrophic failures in analog circuits. The new introduced methodology helps Analog designers to determine the effect of layout interdependencies at early stages of the design by introducing a layout-aware schematic design level. A 45nm Miller OTA design example is given to show the validity of the proposed methodology.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122529089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions 磁隧结非易失性存储电路和磁隧结TAS写入技术
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463536
Victor Silva, M. Véstias, H. Neto, J. Fernandes
{"title":"Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions","authors":"Victor Silva, M. Véstias, H. Neto, J. Fernandes","doi":"10.1109/ICECS.2012.6463536","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463536","url":null,"abstract":"This paper presents, and compares, two circuits based on Magnetic RAM (MRAM) technology for use as configuration memory elements of coarse grained reconfigurable arrays. MRAM based memory cells provide non-volatility with cell areas and access speeds comparable to those of conventional static memories. Two scaled-down prototypes of a coarse grain reconfigurable array that employs MRAM based elements as configuration memory have been designed, manufactured and tested. One prototype employs Field Induced Magnetic Switching (FIMS) writing technique while the other prototype employs Thermally Assisted Switching (TAS) writing technique. Both prototypes are compared qualitatively and quantitatively and conclusions are drawn.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114595868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A switching based adaptive image interpolation algorithm 一种基于开关的自适应图像插值算法
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463525
Nimisha Agarwal, Ayush Kumar, Juhi Bhadviya, A. Tiwari
{"title":"A switching based adaptive image interpolation algorithm","authors":"Nimisha Agarwal, Ayush Kumar, Juhi Bhadviya, A. Tiwari","doi":"10.1109/ICECS.2012.6463525","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463525","url":null,"abstract":"In this paper, we propose a new adaptive image interpolation algorithm for enhancement of natural images. The proposed method uses different algorithms namely SAI, SPIA and Context-Based Image Interpolation Algorithm (CBIA) techniques, for both edgy and smooth type of images. The detailed part of smooth type image is interpolated by SAI, while we propose to use SPIA method for detailed part of edgy image. The rest of the pixels for either type of images are interpolated by CBIA. From the simulation results, we found that our adaptive interpolation technique results in better subjective and objective (PSNR) quality in comparision to some of the recent works in literature.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129341282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Adaptive slope and threshold companding technique for PAPR reduction in OFDM systems OFDM系统中减小PAPR的自适应斜率和阈值扩展技术
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463739
Vivek Yenamandra, Feiran Lei, S. Al-Araji, N. Ali, M. Ismail
{"title":"Adaptive slope and threshold companding technique for PAPR reduction in OFDM systems","authors":"Vivek Yenamandra, Feiran Lei, S. Al-Araji, N. Ali, M. Ismail","doi":"10.1109/ICECS.2012.6463739","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463739","url":null,"abstract":"High Peak to Average Power Ratio (PAPR) of transmitted signals is a major drawback for multi-carrier modulation systems such as orthogonal frequency division multiplexing (OFDM) systems. Companding technique has been recently used to reduce PAPR. In this work, an adaptive slope and threshold (AST) companding transform is proposed to increase the reduction in PAPR with minimum degradation of received bit error rate (BER). The key idea is to adaptively vary both the slope of expansion and the threshold for expansion of the input signal amplitude to optimize the PAPR/BER tradeoff. This is implemented by selecting slope and threshold ratios in real-time from a look-up table (LUT) on the basis of the received feedback, making it adaptive.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"29 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129534179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Test setup for error vector magnitude measurement on WLAN transceivers 测试设置的误差矢量测量无线局域网收发器
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463512
V. Fialho, F. Fortes, Manuela Vieira
{"title":"Test setup for error vector magnitude measurement on WLAN transceivers","authors":"V. Fialho, F. Fortes, Manuela Vieira","doi":"10.1109/ICECS.2012.6463512","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463512","url":null,"abstract":"This paper presents a measurement system and experimental examples of error vector magnitude measurements on a wireless local area network receiver under several radio frequency impairments, with emphasis to local oscillator phase noise. An algorithm that cancels the phase and frequency carrier synchronization error is presented. Typical base band figure of merit are obtained under influence of these impairments. The described method allows the experimental calculation of error vector magnitude without a dedicated vector analyzer.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126906188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Embedded low-power low-cost Camera Sensor based on FPGA and its applications in mobile robots 基于FPGA的嵌入式低功耗低成本摄像头传感器及其在移动机器人中的应用
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463733
J. Albó-Canals, S. Ortega, Sergi Perdices, A. Badalov, Xavier Vilasís-Cardona
{"title":"Embedded low-power low-cost Camera Sensor based on FPGA and its applications in mobile robots","authors":"J. Albó-Canals, S. Ortega, Sergi Perdices, A. Badalov, Xavier Vilasís-Cardona","doi":"10.1109/ICECS.2012.6463733","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463733","url":null,"abstract":"In this paper, we present the functionality of a low-cost camera sensor based on FPGAs. It is intended to be a solution for affordable robotic platforms requiring a smart vision sensor. This implies using simple image processing algorithms that are, nevertheless, flexible enough to ensure the robot navigation. The image processing elements and the connectivity both to the camera and the robot are embedded in an Actel Igloo FPGA, which fits the low power consumption, reprogrammability and cost requirements. We also present two applications. The first one, related to path planning, shows how a robot with such a device is able to identify different scenarios in the process of learning how to escape from a maze using reinforcement learning. The second application is a set of interactive activities using a companion robot and requiring robot vision devised to improve the recovery of children with brain trauma. In this particular case, both the cost and power consumption requirements for the camera sensor are demanding, since the robot has to be distributed to a large number of children and low consumption is essential to keep the robot working time within the therapeutic needs.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123686413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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