Layout stress and proximity aware analog design methodology

This paper presents a new methodology for analog circuits design which takes into account layout dependent effects and layout interdependencies between devices. Analog Devices' performance is impacted by other layout features located in near context. These layout effects can lead to catastrophic failures in analog circuits. The new introduced methodology helps Analog designers to determine the effect of layout interdependencies at early stages of the design by introducing a layout-aware schematic design level. A 45nm Miller OTA design example is given to show the validity of the proposed methodology.