2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)最新文献_第2页

A process-compatible passive RFID tag's digital design for subthreshold operation 面向亚阈值操作的过程兼容无源RFID标签数字化设计

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463692

Weiwei Shi, O. Choy

引用次数: 2

Electrical characterization of a C-Element with LiChEn 含地衣C-Element的电学特性

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463680

Matheus T. Moreira, Ney Laert Vilar Calazans

{"title":"Electrical characterization of a C-Element with LiChEn","authors":"Matheus T. Moreira, Ney Laert Vilar Calazans","doi":"10.1109/ICECS.2012.6463680","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463680","url":null,"abstract":"This demonstration presents the use of the Library Characterization Environment (LiChEn) for characterizing asynchronous standard cells. The tool was employed for the electrical characterization of a library with over five hundred asynchronous standard cells. In this work, a case study of a fundamental asynchronous component, the C-Element, will be presented to validate the use of the tool. LiChEn was designed due to the necessity of automating the process of characterizing asynchronous standard cells. Albeit this task can be done with tools from industrial EDA vendors, the use of these proved to require laborious manual work. These tools were designed for characterizing standard cells for synchronous systems and usually fail to recognize complex asynchronous logic. Moreover, asynchronous components are not available off the shelf in typical standard cell libraries, which constrains the asynchronous paradigm for full-custom approaches. As asynchronous techniques gain relevance in the research community, LiChEn can present a practical solution for a wider adoption of such techniques, by allowing an automated characterization of asynchronous standard cells.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121522083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Enhancing performance of MPSoCs through distributed resource management 通过分布式资源管理提高mpsoc的性能

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463689

Marcelo G. Mandelli, Guilherme M. Castilhos, F. Moraes

引用次数: 4

Utilization of multi-bit flip-flops for clock power reduction 利用多比特触发器降低时钟功耗

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463635

Zhi-Wei Chen, Jin-Tai Yan

{"title":"Utilization of multi-bit flip-flops for clock power reduction","authors":"Zhi-Wei Chen, Jin-Tai Yan","doi":"10.1109/ICECS.2012.6463635","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463635","url":null,"abstract":"Utilization of multi-bit flip-flops in a synchronous design has been becoming a significant methodology for clock power reduction. However, some published approaches are usually based on the assumption that the bit number of the flip-flops is continuous or the number of the available flip-flops is infinite in a cell library. Under the physical limitation of the flip-flop cells in a real cell library, the bit number of the flip-flops is discrete and the number of the available flip-flops is finite. In this paper, given a synchronous system with a set of 1-bit flip-flops in a placement plane, the timing constraints of the associated signals in the flip-flops and the available flip-flops in a real cell library, based on the bit number of the available multi-bit flip-flops in the given cell library, an optimal approach is proposed to obtain the maximum power-saving result by merging 1-bit flip-flops into the available flip-flops. Compared with the original synchronous designs using 1-bit flip-flops, the experimental results show that our proposed approach reduces 38.4% of the flip-flop area and saves 24.9% of the clock power to maintain the synchronous property on the average for five tested examples in reasonable CPU time.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127601104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Peak power estimation using activity measured on emulator 利用仿真器测量的活度估计峰值功率

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463655

C. Berthet, P. Georgelin, Janvier Ntyame, Mathieu Raffin

引用次数: 2

Statistical leakage analysis using the deterministic modeling of cell leakage current 利用电池泄漏电流的确定性模型进行统计泄漏分析

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463529

Jae Hoon Kim, Young Hwan Kim

引用次数: 0

Discrete-time simulation of arbitrary digital/analog converter waveforms in continuous-time sigma-delta modulators 连续时间σ - δ调制器中任意数模转换器波形的离散时间仿真

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463657

Timon Brückner, Martin Kiebler, C. Zorn, W. Mathis, M. Ortmanns

引用次数: 4

High-drive capability buffer for highly variable resistive loads 高驱动能力缓冲高可变电阻负载

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463620

E. Covi, A. Cabrini, G. Torelli

引用次数: 0

Protein alignment HW/SW optimizations 蛋白质比对HW/SW优化

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463779

Gianvito Urgese, M. Graziano, M. Vacca, M. Awais, S. Frache, M. Zamboni

引用次数: 16

A generic FPGA emulation framework 一个通用的FPGA仿真框架

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463758

F. Moraes, Matheus T. Moreira, C. Lucas, D. Corrêa, Douglas de O. Cardoso, M. Magnaguagno, Guilherme M. Castilhos, Ney Laert Vilar Calazans

{"title":"A generic FPGA emulation framework","authors":"F. Moraes, Matheus T. Moreira, C. Lucas, D. Corrêa, Douglas de O. Cardoso, M. Magnaguagno, Guilherme M. Castilhos, Ney Laert Vilar Calazans","doi":"10.1109/ICECS.2012.6463758","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463758","url":null,"abstract":"Verification techniques face growing challenges, as digital system design becomes increasingly complex. Currently, verification is believed to be the main bottleneck for expedite complex designs, consuming at least 70% of the whole system development effort. This paper proposes a new, generic hardware emulation framework to improve the observability of designs as well as reducing emulation-based verification intrusiveness. The proposed emulator provides enhanced observability and controllability of inner workings of the system when compared to commercial FPGA-based emulators and is less intrusive on the design under verification. As FPGA-vendor specific products, the proposed emulator is generic, supporting in principle any digital system design. To enhance flexibility, stimuli generation and response capture is under control of a host computer and communication between the host and the design under verification may occur through an Ethernet interface or through PCIe interfaces in supported platforms. The prototype of the proposed framework is operational and presents promising results in terms of observability and controllability enhancement, although further work is needed to improve the framework emulation performance.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"10 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130254369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7