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2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)最新文献

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Complements on phase noise analysis and design of CMOS ring oscillators 补充了CMOS环形振荡器的相位噪声分析和设计
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463540
Timothy Cronin, D. Pepe, D. Zito
{"title":"Complements on phase noise analysis and design of CMOS ring oscillators","authors":"Timothy Cronin, D. Pepe, D. Zito","doi":"10.1109/ICECS.2012.6463540","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463540","url":null,"abstract":"This paper reports two complements on phase noise analysis and design of CMOS ring oscillators. In detail, it proposes an extension to current analytical methods for predicting flicker noise contribution to phase noise in differential CMOS ring oscillators. The results of the proposed analysis are compared with the existing methods and simulation results by SpectreRF for two differential topologies. The comparative analyses confirm that the proposed method leads to an improvement of the prediction accuracy in spite of the small increase of complexity since it only requires device dimensions in addition to the data required by existing methods. The proposed method may also be used to indicate a minimum achievable close-in phase noise in a process node. Moreover, a design approach for low phase noise inverter-based ring oscillator is proposed and tested by means of simulation. The limitations of the proposed method can be observed from this case study.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125996311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Dynamic tree-depth adjustment for low power HEVC encoders 动态树深度调整低功率HEVC编码器
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463684
G. Corrêa, P. Assunção, L. Cruz, L. Agostini
{"title":"Dynamic tree-depth adjustment for low power HEVC encoders","authors":"G. Corrêa, P. Assunção, L. Cruz, L. Agostini","doi":"10.1109/ICECS.2012.6463684","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463684","url":null,"abstract":"Power consumption is a major problem in multimedia-capable mobile devices, especially those equipped with the most advanced video codecs. The emerging HEVC standard introduces a set of features which significantly increase the encoder computational complexity and consequently the power consumption in comparison to its predecessor, H.264/AVC. This paper presents two complexity reduction methods that selectively constrain the coding tree depth to keep computational complexity below a pre-established limit. Experimental results show that the encoder complexity can be reduced to 60% of the original complexity, allowing the implementation of low power HEVC encoders with small or negligible loss in rate-distortion performance.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125165694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Conflict free, parallel memory access for radix-2 FFT processors 无冲突，并行内存访问的基数2 FFT处理器
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463527
Nikolaos Polychronakis, D. Reisis, Emmanouil Tsilis, Ioannis Zokas
{"title":"Conflict free, parallel memory access for radix-2 FFT processors","authors":"Nikolaos Polychronakis, D. Reisis, Emmanouil Tsilis, Ioannis Zokas","doi":"10.1109/ICECS.2012.6463527","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463527","url":null,"abstract":"The current paper presents a parallel addressing technique for radix-2 FFT architectures. The novel technique bases on a permutation to accomplish parallel load and store of the FFT data even with a single memory bank, which stores two FFT elements at each address. Furthermore, the proposed addressing scheme minimizes the requirements for the address generation and processor control circuits. An example FPGA implementation shows the simplicity of the architecture and validates the results.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123591017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Encoding sequence design for a reduced complexity time synchronization approach for OFDM systems 一种降低OFDM系统时间同步复杂度的编码序列设计
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463513
Leila Nasraoui, L. N. Atallah, M. Siala
{"title":"Encoding sequence design for a reduced complexity time synchronization approach for OFDM systems","authors":"Leila Nasraoui, L. N. Atallah, M. Siala","doi":"10.1109/ICECS.2012.6463513","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463513","url":null,"abstract":"We here deal with a recently proposed data-aided reduced-complexity approach for OFDM time synchronization. In the considered approach, an encoding sequence generated from the preamble is differentially correlated with the received signal to estimate the frame start. In this paper, we study the off-line design of the encoding sequence. We present two efficient algorithms for deriving QPSK encoding sequence that allows replacing the differential correlation process, characterized by its high complexity, by a simple sign change. The resulting quantified encoding sequence performs well in both AWGN and multipath channels, compared to the optimal, previously used, encoding sequence. Furthermore, the complexity involved for the metric calculation, using the herein proposed encoding sequence, is reduced considerably by applying the sign change operations. The simulation results show that the use of sub-optimal sequence gives near best detection performances which are provided by the optimal sequence with lower complexity.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123831529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A CMOS track-and-hold circuit with beyond 30 GHz input bandwidth 一种输入带宽超过30ghz的CMOS跟踪保持电路
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463786
B. Sedighi, A. Huynh, E. Skafidas
{"title":"A CMOS track-and-hold circuit with beyond 30 GHz input bandwidth","authors":"B. Sedighi, A. Huynh, E. Skafidas","doi":"10.1109/ICECS.2012.6463786","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463786","url":null,"abstract":"To realize future ultra high-speed data converters, sampling circuits with very large bandwidth are required. This paper studies the design of ultra high-speed Track-and-Hold (T/H) circuits. A bootstrapping circuit for T/H is presented. The proposed T/H is simulated in 32 nm SOI-CMOS technology. It achieves an input bandwidth higher than 30 GHz and provides an SNDR higher than 43.8 dB (ENOB > 7.0 b) when sampling a 34 GHz input signal at 10 GS/s.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126467116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 4-bit 1.5GSps 4.2mW comparator-based binary search ADC in 90nm 一个基于4位1.5GSps 4.2mW比较器的90纳米二进制搜索ADC
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463700
T. Rabuske, Fabio Gibran Rabuske, J. Fernandes, C. Rodrigues
{"title":"A 4-bit 1.5GSps 4.2mW comparator-based binary search ADC in 90nm","authors":"T. Rabuske, Fabio Gibran Rabuske, J. Fernandes, C. Rodrigues","doi":"10.1109/ICECS.2012.6463700","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463700","url":null,"abstract":"Traditional ADC architectures often fail to provide the required balance between low-power and high sampling rate, leaving room for further topology exploration. We propose a modified binary search ADC topology, which relies on a pipeline for the comparator stages and tracks the input in a time-interleaved fashion. Extensive statistical simulations for the 4-bit proposed ADC show that, sampling at 1.5GSps, the ADC consumes 4.2mW, providing 3.67 effective bits and a figure of merit of 219fJ/conversion step, without requiring calibration.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131757864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Analysis of coupling capacitance between TSVs and metal interconnects in 3D-ICs 3d - ic中tsv与金属互连的耦合电容分析
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463647
K. Salah
{"title":"Analysis of coupling capacitance between TSVs and metal interconnects in 3D-ICs","authors":"K. Salah","doi":"10.1109/ICECS.2012.6463647","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463647","url":null,"abstract":"Through-Silicon Via (TSV) is an emerging technology that enables vertical integration of silicon dies forming a single 3D-IC stack. In this paper, the electrical characteristics of coupling between TSVs and metal lines in 3D-ICs are analyzed. The simulation results for the electrical characteristics of the coupling between TSVs and metal lines in 3D-ICs show that the coupling is not negligible when TSV is relatively short compared to the TSV width, where the aspect ratio is less than 5. Therefore, TSV-to-wire capacitance needs to be considered for the computation of TSV capacitance. But, if the aspect ratio is larger than 5, the effect of metal wires is not considered. Moreover, the effect of metal lines on TSV-TSV coupling can be neglected if the pitch is less than 3x the TSV diameter.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129518758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Dedicated FPGA communication architecture and design for a large-scale neuromorphic system 大型神经形态系统专用FPGA通信架构与设计
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463548
V. Thanasoulis, J. Partzsch, S. Hartmann, C. Mayr, R. Schüffny
{"title":"Dedicated FPGA communication architecture and design for a large-scale neuromorphic system","authors":"V. Thanasoulis, J. Partzsch, S. Hartmann, C. Mayr, R. Schüffny","doi":"10.1109/ICECS.2012.6463548","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463548","url":null,"abstract":"The communication infrastructure is a crucial part of neuromorphic VLSI systems. A sophisticated network is required for the transmission of pulse events among the individual neuron-and-synapse circuits and the configuration data for the components of the system. We present a packet-based communication network implemented on FPGA that provides pulse stimulation, inter-node connectivity and allows the complete control and configuration of the neuromorphic system by a host unit. The design deploys a specific architecture for optimized throughput and implements a reliable and ordered data delivery. It employs also a large Playback/Trace memory that offers pulse event replay and recording of the produced neuronal activity. Altogether, our implementation is more versatile than recent FPGA-based neuromorphic infrastructures, allowing for fast system configuration, stimulation and monitoring.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133482401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 7GHz wideband self-correcting quadrature VCO 7GHz宽带自校正正交压控振荡器
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463798
T. Arai, A. Hajimiri
{"title":"A 7GHz wideband self-correcting quadrature VCO","authors":"T. Arai, A. Hajimiri","doi":"10.1109/ICECS.2012.6463798","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463798","url":null,"abstract":"A 4.0 to 6.6GHz self-correcting quadrature voltage controlled oscillator (QVCO) with phase compensation loop is implemented in a 65nm CMOS process. The topology couples IQ oscillation signals of two LC-VCOs, a phase shifter, and buffers with circular configuration. This paper introduces the idea to obtain low phase noise and accurate IQ phase quadrature oscillation signal, by employing phase compensation loop to correct the IQ phase error. The self-correcting QVCO achieves the IQ phase error less than a degree, and 1MHz offset phase noise -107dBc/Hz at 6.9GHz.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"76 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132124942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A monitoring infrastructure for FPGA self-awareness and dynamic adaptation 一种FPGA自感知和动态自适应监控架构
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) Pub Date : 2012-12-01 DOI: 10.1109/ICECS.2012.6463547
C. Osuna, M. A. S. Marcos, P. Ituero, M. López-Vallejo
{"title":"A monitoring infrastructure for FPGA self-awareness and dynamic adaptation","authors":"C. Osuna, M. A. S. Marcos, P. Ituero, M. López-Vallejo","doi":"10.1109/ICECS.2012.6463547","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463547","url":null,"abstract":"Variabilities associated with CMOS evolution affect the yield and performance of current digital designs. FPGAs, which are widely used for fast prototyping and implementation of digital circuits, also suffer from these issues. Proactive approaches start to appear to achieve self-awareness and dynamic adaptation of these devices. To support these techniques we propose the employment of a multi-purpose sensor network. This infrastructure, through adequate use of configuration and automation tools, is able to obtain relevant data along the life cycle of an FPGA. This is realised at a very reduced cost, not only in terms of area or other limited resources, but also regarding the design effort required to define and deploy the measuring infrastructure. Our proposal has been validated by measuring inter-die and intra-die variability in different FPGA families.","PeriodicalId":269365,"journal":{"name":"2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129447153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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