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Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.最新文献

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A novel CMOS temperature control system for resistive gas sensor arrays 一种用于电阻式气体传感器阵列的新型CMOS温度控制系统
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523052
G. Ferri, N. Guerrini, V. Stornelli, C. Catalani
{"title":"A novel CMOS temperature control system for resistive gas sensor arrays","authors":"G. Ferri, N. Guerrini, V. Stornelli, C. Catalani","doi":"10.1109/ECCTD.2005.1523052","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523052","url":null,"abstract":"A novel CMOS integrated system for the temperature control of resistive gas sensor interfaces is presented. It is formed by a sensor heater (which controls the sensor temperature), a resistance-to-frequency converter and digital control logic.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115298975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Analytical approach for analyzing tapered transmission lines 锥形传输线的分析方法
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523090
Behnam Faraji, Mohammad Hadi Eghlidi, K. Mehrany, B. Rashidian
{"title":"Analytical approach for analyzing tapered transmission lines","authors":"Behnam Faraji, Mohammad Hadi Eghlidi, K. Mehrany, B. Rashidian","doi":"10.1109/ECCTD.2005.1523090","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523090","url":null,"abstract":"A new analytical method is introduced for the analysis of wave propagation in one-dimensional tapered transmission lines. Based on the analytical extension of ordinary transfer matrix into differential transfer matrix, this approach can be used for calculating reflection and transmission coefficients. Different numerical test cases are thoroughly studied and in each case an excellent agreement between the results of our differential transfer matrix method and exact solutions is observed. It is also shown that our approach is superior to the more common small reflection method.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"25 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115364620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A detailed complexity model for multiple constant multiplication and an algorithm to minimize the complexity 详细的多常数乘法的复杂度模型和最小化复杂度的算法
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523161
K. Johansson, O. Gustafsson, L. Wanhammar
{"title":"A detailed complexity model for multiple constant multiplication and an algorithm to minimize the complexity","authors":"K. Johansson, O. Gustafsson, L. Wanhammar","doi":"10.1109/ECCTD.2005.1523161","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523161","url":null,"abstract":"Multiple constant multiplication (MCM) has been an active research area for the last decade. Most work so far have only considered the number of additions to realize a number of constant multiplications with the same input. In this work, we consider the number of full and half adder cells required to realize those additions, and a novel complexity measure is proposed. The proposed complexity measure can be utilized for all types of constant operations based on shifts, additions and subtractions. Based on the proposed complexity measure a novel MCM algorithm is presented. Simulations show that compared with previous algorithms, the proposed MCM algorithm have a similar number of additions while the number of full adder cells are significantly reduced.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115706743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
A design scheme for sampling switch in active matrix LCD 有源矩阵液晶显示器中采样开关的设计方案
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1522985
Shingo Takahashi, Akira Taji, S. Tsukiyama, M. Hashimoto, I. Shirakawa
{"title":"A design scheme for sampling switch in active matrix LCD","authors":"Shingo Takahashi, Akira Taji, S. Tsukiyama, M. Hashimoto, I. Shirakawa","doi":"10.1109/ECCTD.2005.1522985","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1522985","url":null,"abstract":"In the design of a source driver in an active matrix LCD, of primal importance is the issue of how to restrict the admissible allowance of the RPV (i.e. the ratio of the pixel voltage to the video voltage) of a pixel within a specified narrow range, which determines the transmitted luminance of the pixel. This constraint on the RPV is analyzed in terms of parameters associated with the sampling switch and the sampling pulse, and then by using a minimal number of these parameters, a design scheme is described dedicatedly for the sampling switch. Experimental results show that an optimal sampling switch can be attained by the proposed scheme, which gives rise to a source driver with almost 50% less power consumption than the one by manual design.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127363502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low power, low complexity CMOS multiple-input replicating current comparators and WTA/LTA circuits 低功耗，低复杂度CMOS多输入复制电流比较器和WTA/LTA电路
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523105
B. Tomatsopoulos, A. Demosthenous
{"title":"Low power, low complexity CMOS multiple-input replicating current comparators and WTA/LTA circuits","authors":"B. Tomatsopoulos, A. Demosthenous","doi":"10.1109/ECCTD.2005.1523105","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523105","url":null,"abstract":"This paper presents an overview of low power, low complexity and high speed CMOS synchronous replicating current comparators (RCC) for use in any analog and digital signal processors. Although 2-input synchronous RCCs have been reported in the literature, multiple input versions tend to be power hungry and usually suffer from accumulated errors. On the other hand, asynchronous RCCs impose speed limitations and require large supply rails. This paper presents a new structure for a simultaneous multiple input RCC. The circuit can also be used to perform loser/winner-take-all (LTA/WTA) operations. Simulation results for an 8-input RCC show that a resolution of 1 μA can be achieved for an input range of 5-70 μA, consuming 2.27 mW from a 3 V supply at 20 MHz.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116108969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A slow-fast dynamics model of a second-order logdomain floating-capacitor LC-ladder circuit 二阶对数域浮电容lc阶梯电路的慢快动力学模型
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1522979
A. Ascoli, P. Curran, O. Feely
{"title":"A slow-fast dynamics model of a second-order logdomain floating-capacitor LC-ladder circuit","authors":"A. Ascoli, P. Curran, O. Feely","doi":"10.1109/ECCTD.2005.1522979","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1522979","url":null,"abstract":"∗ Department of Electronic Engineering, University College Dublin, Belfield, Dublin 4, Ireland, e-mails: [alon.ascoli, paul.curran, orla.feely]@ucd.ie, tel.: +353 17161913, fax: +353 1 2830921. Abstract − A common assumption in log-domain circuit theory is that bipolar junction transistors behave as static exponential nonlinearities. Zero-input limit-cycle oscillations were recently observed at the output of a second-order floating-capacitor log-domain LC-ladder filter under particular conditions. Modeling each transistor as a static exponential nonlinearity, the corresponding circuit equations fail to describe these dynamics. This paper presents a transistor dynamic model, which, taking into account the parasitic capacitances, explains the external nonlinear behavior under investigation.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116130964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Output power control in a power combiner with class-DE amplifiers 带de类放大器的功率组合器的输出功率控制
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523076
J. Modzelewski, M. Mikolajewski
{"title":"Output power control in a power combiner with class-DE amplifiers","authors":"J. Modzelewski, M. Mikolajewski","doi":"10.1109/ECCTD.2005.1523076","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523076","url":null,"abstract":"Output power of transistorised high-power high-frequency converters can be controlled utilising their specific structure consisting of a set of amplifiers the power of which is combined. The output power of such a converter can be controlled by varying the number of combined amplifiers versus the control signal. In the controlled power-combining network there can be used class-DE power amplifiers operating in zero-voltage-switching conditions, which assures high efficiency for any nonzero output power. The paper presents a theoretical analysis for a power-combining converter with class-DE amplifiers and experimental results obtained for a five-stage 500kHz/700W laboratory model. Advantages and limitations of the power-control method are also discussed.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122729308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Compact model for a cantilever beam MEM contact switch 悬臂梁MEM触点开关的紧凑模型
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1522906
T. Veijola
{"title":"Compact model for a cantilever beam MEM contact switch","authors":"T. Veijola","doi":"10.1109/ECCTD.2005.1522906","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1522906","url":null,"abstract":"A compact model for a cantilever beam microelectromechanical (MEM) contact switch is constructed. The beam deflection is modeled by discretizing the beam along its length. The distributed capacitance, electrostatic force and squeezed-film fluid force are also calculated at the same discrete points. The electromechanical contact tip is modeled as a lumped contact force and conductance. The model is implemented with a nonlinear equivalent circuit utilizing the components in the MEMS module of the circuit simulation and design tool Aplac. This enables nonlinear time and frequency domain simulations. This paper presents transient on/off characteristics simulations, and analyses and compares the S-parameters at the on- and off-positions.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122803090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Optimised Montgomery domain inversion on FPGA 基于FPGA的Montgomery域反演优化
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1522964
F. Lau, A. Daly, W. Marnane
{"title":"Optimised Montgomery domain inversion on FPGA","authors":"F. Lau, A. Daly, W. Marnane","doi":"10.1109/ECCTD.2005.1522964","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1522964","url":null,"abstract":"Modular inversion is a critical operation in elliptic curve cryptosystems (ECC). This paper presents a hardware optimised modular inversion algorithm targeted towards an FPGA implementation. It exploits the underlying structure of the device, leading to a fast and efficient design. Arithmetic is performed in the Montgomery domain, which allows an inversion result to be an input to further operations without the need for domain conversion. Results presented show an increase in throughput over existing inverter designs on reconfigurable logic.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122480750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Innovation to overcome limitations of test equipment 创新以克服测试设备的局限性
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1522972
C. Wegener, Michael Peter Kennedy
{"title":"Innovation to overcome limitations of test equipment","authors":"C. Wegener, Michael Peter Kennedy","doi":"10.1109/ECCTD.2005.1522972","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1522972","url":null,"abstract":"In this contribution, we describe current developments in the automatic test equipment (ATE) industry with respect to the hardware and software. For testing mixed-signal interface devices, such as digital-to-analog and analog-to-digital converters (DACs and ADCs) the standard test setups are examined. In particular, limitations are identified that lead to exponentially increasing test time for high-resolution converters. Examples of innovative approaches to keep this test cost increase at bay are outlined.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122994305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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