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Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.最新文献

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Power-balanced asynchronous logic 功率平衡异步逻辑
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523031
Julian P. Murphy, A. Yakovlev
{"title":"Power-balanced asynchronous logic","authors":"Julian P. Murphy, A. Yakovlev","doi":"10.1109/ECCTD.2005.1523031","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523031","url":null,"abstract":"The susceptibility of cryptographic devices to power analysis has proved to be a significant security risk, and is becoming increasingly mainstream stemming from the make-up of all devices - CMOS logic. This paper proposes using asynchronous logic, enhanced to be power-balanced, to design devices resistant to power analysis.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132525163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A mixed-mode conditioning circuit designed for adaptive smart sensing 一种用于自适应智能传感的混合模式调理电路
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523099
G. Zatorre, N. Medrano-Marqués, S. Celma
{"title":"A mixed-mode conditioning circuit designed for adaptive smart sensing","authors":"G. Zatorre, N. Medrano-Marqués, S. Celma","doi":"10.1109/ECCTD.2005.1523099","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523099","url":null,"abstract":"This paper explains the design and simulation of a conditioning circuit based on a current-mode mixed analogue-digital adaptive processor. The proposed processor model consists of two main blocks: a D/A four quadrant multiplier and a current conveyor that performs the non-linear output function. Applied to sensors conditioning, the processing system customizes its free parameters, stored in digital registers, adapting the response. System simulation results and achieved performance are presented.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116050992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
One-dimensional discrete-time dynamical systems circuit using floating-gate MOS peaking current sink/source 利用浮栅MOS峰值电流汇/源的一维离散动力系统电路
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1522897
Tomoumi Yagasaki, Y. Horio, K. Aihara
{"title":"One-dimensional discrete-time dynamical systems circuit using floating-gate MOS peaking current sink/source","authors":"Tomoumi Yagasaki, Y. Horio, K. Aihara","doi":"10.1109/ECCTD.2005.1522897","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1522897","url":null,"abstract":"This paper proposes a one-dimensional discrete-time dynamical systems circuit exploiting the nonlinear transfer characteristic of the MOS peaking current sink/source as a mapping function. The proposed circuit can produce a variety of dynamics because we use floating-gate MOSFETs in the MOS peaking current sink/source circuits so that their transfer characteristics can be easily altered externally. Moreover, the proposed circuit is insensitive to the parasitic charges on the floating-gates. Return maps and bifurcation diagrams obtained through HSPICE simulations are demonstrated.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132194253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A realization of FIR system for on-line writer recognition FIR在线作家识别系统的实现
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1522974
T. Matsuura, Kazuki Izumi
{"title":"A realization of FIR system for on-line writer recognition","authors":"T. Matsuura, Kazuki Izumi","doi":"10.1109/ECCTD.2005.1522974","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1522974","url":null,"abstract":"This paper presents a realization of finite impulse response (FIR) system for on-line writer recognition. The FIR system is realized using Fourier coefficients of a barycenter of trajectory of pen-tip movement (BTP) and its velocity in handwriting process. The input and output of the FIR system are the Fourier coefficients of the velocity and the BTP, respectively. With the realized FIR system, writer can be recognized by comparing the output to the input for unknown writer with the reference output for a particular writer. Experimental results are given to show the effectiveness of the proposed method. In our experiments, FRR (false rejection rate) and FAR (false acceptance rate) were 1.50% and 0.65%, respectively.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128529340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A complete front-end system read-out and temperature control for resistive gas sensor array 一个完整的前端系统读出和温度控制电阻气体传感器阵列
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523053
M. Malfatti, M. Perenzoni, Nicola Viarani, A. Simoni, L. Lorenzelli, A. Baschirotto
{"title":"A complete front-end system read-out and temperature control for resistive gas sensor array","authors":"M. Malfatti, M. Perenzoni, Nicola Viarani, A. Simoni, L. Lorenzelli, A. Baschirotto","doi":"10.1109/ECCTD.2005.1523053","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523053","url":null,"abstract":"A complete front-end system for resistive gas sensor array is presented. The system is composed by a substrate temperature control circuit and by a read-out circuit. The temperature control allows maintaining a 100/spl deg/C temperature gradient selected in the temperature range [150/spl deg/C-350/spl deg/C] on the array of sensor. The gas sensor read-out circuit, which acts like a resistance-to-period converter, is suitable to be interfaced to a microcontroller in order to achieve a resolution error lower than 0.5% for a resistance ranging in (300k/spl Omega/-300M/spl Omega/]. The full device, including 8 read-out channels and 2 temperature control systems, is designed in a standard 0.35/spl mu/m CMOS technology. The die area is 1.8mm/sup 2/ with a total power consumption of 30mW from a single 3.3V supply voltage.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132795414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Real time vision by FPGA implemented CNNs 通过FPGA实现cnn的实时视觉
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1522965
J. C. López-García, M. Moreno-Armendáriz, J. Riera-Babures, M. Balsi, X. Vilasís-Cardona
{"title":"Real time vision by FPGA implemented CNNs","authors":"J. C. López-García, M. Moreno-Armendáriz, J. Riera-Babures, M. Balsi, X. Vilasís-Cardona","doi":"10.1109/ECCTD.2005.1522965","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1522965","url":null,"abstract":"In order to get real time image processing for mobile robot vision, we propose to use a discrete time cellular neural network implementation by a convolutional structure on Altora FPGA using VHDL language. We obtain at least 9 times faster processing than other emulations for the same problem.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134326792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A new multi-mode multifunction filter using CDBA 基于CDBA的多模多功能滤波器
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523034
M. Sagbas, Muhammet Köksal
{"title":"A new multi-mode multifunction filter using CDBA","authors":"M. Sagbas, Muhammet Köksal","doi":"10.1109/ECCTD.2005.1523034","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523034","url":null,"abstract":"A new multi-mode multifunction filter using CDBA is proposed. The original filter has a single current input and three voltage outputs and operates in transimpedance-mode. It can generate all biquadratic filter functions of low-pass, high-pass and band-pass, and also band-reject and all-pass filter responses by selecting different output signal combinations. This filter can be converted into voltage-mode by an additional input resistor. It can also be used in current-mode at the output by using one extra load resistor at each output. With these additional resistors at the input and outputs the filter operates in transadmittance-mode. The structure of the new filter proposed contains two capacitors, three resistors and three CDBAs.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"66 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126978957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
New analytical approach to evaluate harmonic distortion in nonlinear feedback amplifiers 评估非线性反馈放大器谐波失真的新分析方法
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523069
S. Cannizzaro, G. Palumbo, S. Pennisi
{"title":"New analytical approach to evaluate harmonic distortion in nonlinear feedback amplifiers","authors":"S. Cannizzaro, G. Palumbo, S. Pennisi","doi":"10.1109/ECCTD.2005.1523069","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523069","url":null,"abstract":"In this contribution we present a simple method to evaluate harmonic distortion in the frequency domain of amplifiers embedded in a generic nonlinear feedback network. The closed-form expressions obtained are accurate and extend our understanding of nonlinear frequency behavior in general feedback circuits. As an example, linearity of an active-RC integrator is considered and analyzed in detail. The suitability of the proposed approach was confirmed by comparison with computer simulations.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"49 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121721718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Simple CMOS 1/jL/spl omega/ to inductive transconductance amplifier 简单的CMOS 1/jL/spl欧米茄/感应跨导放大器
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523127
H. Barthélemy, M. Fillaud
{"title":"Simple CMOS 1/jL/spl omega/ to inductive transconductance amplifier","authors":"H. Barthélemy, M. Fillaud","doi":"10.1109/ECCTD.2005.1523127","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523127","url":null,"abstract":"A continuous-time inductive (1/jL/spl omega/) CMOS transconductance analog amplifier is presented. The proposed CMOS amplifier contains one capacitor and eleven transistors only. The circuit based on a modified traditional gyrator simulates an inductive transconductance. Simulation results under 2.5V supply voltage and using the 0.8/spl mu/m CMOS process parameters from AMS have shown good performances. For example, from a DC bias current of 10 /spl mu/A to 50 /spl mu/A, the controlled inductance (L/sub x/) that defines the amplifier transconductance varies from L/sub x/=406 /spl mu/H to L/sub x/=47 /spl mu/H. At 50 /spl mu/A the total power consumption is 634 /spl mu/W only. Based on this new topology, additional simulation results of a simple current-controlled band-pass filter have been added in this paper.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125244485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modulo 2/sup n/ - 1 multiplication/sum-of-squares units 模2/sup (n/ - 1)乘以/平方和单位
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523013
D. Adamidis, H. T. Vergos
{"title":"Modulo 2/sup n/ - 1 multiplication/sum-of-squares units","authors":"D. Adamidis, H. T. Vergos","doi":"10.1109/ECCTD.2005.1523013","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523013","url":null,"abstract":"Several applications profit from the use of a residue number system (RNS). Moduli of the 2/sup n/ - 1 form are among the most commonly used in such systems in which the multiplication and sum-of-squares operations are commonly met. These operations are currently performed using distinct design units and consecutive machine cycles. In this paper, we propose two architectures for modulo 2/sup n/ - 1 units that perform either the X /spl times/ Y or X/sup 2/ + Y/sup 2/ operation depending on the value of a control signal.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125172296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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