A slow-fast dynamics model of a second-order logdomain floating-capacitor LC-ladder circuit

A. Ascoli, P. Curran, O. Feely
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引用次数: 1

Abstract

∗ Department of Electronic Engineering, University College Dublin, Belfield, Dublin 4, Ireland, e-mails: [alon.ascoli, paul.curran, orla.feely]@ucd.ie, tel.: +353 17161913, fax: +353 1 2830921. Abstract − A common assumption in log-domain circuit theory is that bipolar junction transistors behave as static exponential nonlinearities. Zero-input limit-cycle oscillations were recently observed at the output of a second-order floating-capacitor log-domain LC-ladder filter under particular conditions. Modeling each transistor as a static exponential nonlinearity, the corresponding circuit equations fail to describe these dynamics. This paper presents a transistor dynamic model, which, taking into account the parasitic capacitances, explains the external nonlinear behavior under investigation.
二阶对数域浮电容lc阶梯电路的慢快动力学模型
*都柏林大学电子工程系,贝尔菲尔德,都柏林4,爱尔兰,电子邮件:[单独]。阿斯科利,保罗。伦,orla.feely @ucd。即,电话:+353 17161913,传真:+353 1 2830921。−在对数域电路理论中,一个常见的假设是双极结晶体管表现为静态指数非线性。在特定条件下,在二阶浮电容对数域lc阶梯滤波器的输出处观察到零输入极限环振荡。将每个晶体管建模为静态指数非线性,相应的电路方程无法描述这些动态。本文提出了一个考虑寄生电容的晶体管动态模型,该模型解释了所研究的外部非线性行为。
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