{"title":"A slow-fast dynamics model of a second-order logdomain floating-capacitor LC-ladder circuit","authors":"A. Ascoli, P. Curran, O. Feely","doi":"10.1109/ECCTD.2005.1522979","DOIUrl":null,"url":null,"abstract":"∗ Department of Electronic Engineering, University College Dublin, Belfield, Dublin 4, Ireland, e-mails: [alon.ascoli, paul.curran, orla.feely]@ucd.ie, tel.: +353 17161913, fax: +353 1 2830921. Abstract − A common assumption in log-domain circuit theory is that bipolar junction transistors behave as static exponential nonlinearities. Zero-input limit-cycle oscillations were recently observed at the output of a second-order floating-capacitor log-domain LC-ladder filter under particular conditions. Modeling each transistor as a static exponential nonlinearity, the corresponding circuit equations fail to describe these dynamics. This paper presents a transistor dynamic model, which, taking into account the parasitic capacitances, explains the external nonlinear behavior under investigation.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2005.1522979","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
∗ Department of Electronic Engineering, University College Dublin, Belfield, Dublin 4, Ireland, e-mails: [alon.ascoli, paul.curran, orla.feely]@ucd.ie, tel.: +353 17161913, fax: +353 1 2830921. Abstract − A common assumption in log-domain circuit theory is that bipolar junction transistors behave as static exponential nonlinearities. Zero-input limit-cycle oscillations were recently observed at the output of a second-order floating-capacitor log-domain LC-ladder filter under particular conditions. Modeling each transistor as a static exponential nonlinearity, the corresponding circuit equations fail to describe these dynamics. This paper presents a transistor dynamic model, which, taking into account the parasitic capacitances, explains the external nonlinear behavior under investigation.