Low power, low complexity CMOS multiple-input replicating current comparators and WTA/LTA circuits

Abstract

This paper presents an overview of low power, low complexity and high speed CMOS synchronous replicating current comparators (RCC) for use in any analog and digital signal processors. Although 2-input synchronous RCCs have been reported in the literature, multiple input versions tend to be power hungry and usually suffer from accumulated errors. On the other hand, asynchronous RCCs impose speed limitations and require large supply rails. This paper presents a new structure for a simultaneous multiple input RCC. The circuit can also be used to perform loser/winner-take-all (LTA/WTA) operations. Simulation results for an 8-input RCC show that a resolution of 1 μA can be achieved for an input range of 5-70 μA, consuming 2.27 mW from a 3 V supply at 20 MHz.