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Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.最新文献

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Route to chaos in an opto-electronic system 光电系统的混沌路径
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523018
L. Larger, D. Fournier-Prunaret
{"title":"Route to chaos in an opto-electronic system","authors":"L. Larger, D. Fournier-Prunaret","doi":"10.1109/ECCTD.2005.1523018","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523018","url":null,"abstract":"An optoelectronic nonlinear delay oscillator seeded by a pulsed laser source is reported. It produces a chaotic optical phase modulation, which can be modeled by a map. The setup is able to operate at high repetition rate with a differential phase modulation of optical pulses. It is intended for high speed digital data encryption at the physical layer using a chaotic optical carrier. Different possible behaviors are analyzed in terms of nonlinear dynamics.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"2021 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116865402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
OTA-C lowpass design using evolutionary algorithms 采用进化算法的OTA-C低通设计
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523027
D. Ticha, P. Martínek
{"title":"OTA-C lowpass design using evolutionary algorithms","authors":"D. Ticha, P. Martínek","doi":"10.1109/ECCTD.2005.1523027","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523027","url":null,"abstract":"The paper proposes a non-conventional design of OTA-C low-pass filter including multi-criterion optimization of final filter structure parameters. The optimization procedure is based on the Differential Evolutionary Algorithms usage and allows simultaneously to minimize filter element values spread and to optimize dynamic properties of filter structure. The basic features of the used algorithms are presented. The design procedure is illustrated by a numerical example of the 5th-order Cauer LP filter.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128214336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
On cellular neural network learning 关于细胞神经网络学习
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1522933
X. Vilasís-Cardona, M. Vinyoles-Serra
{"title":"On cellular neural network learning","authors":"X. Vilasís-Cardona, M. Vinyoles-Serra","doi":"10.1109/ECCTD.2005.1522933","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1522933","url":null,"abstract":"We study the continuous time two neuron CNN in the context of a supervised learning problem and extract the convergence map for constant inputs. From this result we can design a CNN cloning template for a classification problem. Some of the parameters of this cloning template play no effective role in the tesselation giving the convergence map. This gives some hints on how to set up a learning problem and solves the template composition problem for this case.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128425860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design techniques for high performance CMOS flash analog-to-digital converters 高性能CMOS闪存模数转换器的设计技术
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1522927
Sunghyun Park, M. Flynn
{"title":"Design techniques for high performance CMOS flash analog-to-digital converters","authors":"Sunghyun Park, M. Flynn","doi":"10.1109/ECCTD.2005.1522927","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1522927","url":null,"abstract":"This paper reviews the limitations in the performance of CMOS flash ADCs. Methods to enhance sampling rate, such as interleaving and latch cascading, are discussed, and a method that employs inductors to improve comparator performance is presented. We also consider the benefits and trade-offs of implementing a flash ADC without a track-and-hold.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128963103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A method for compensating the D/A converter frequency response distortion in OFDM system OFDM系统中D/A转换器频率响应失真的补偿方法
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523040
Olli Väänänen, M. Kaltiokallio, J. Vankka, K. Halonen
{"title":"A method for compensating the D/A converter frequency response distortion in OFDM system","authors":"Olli Väänänen, M. Kaltiokallio, J. Vankka, K. Halonen","doi":"10.1109/ECCTD.2005.1523040","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523040","url":null,"abstract":"A method to compensate the sine effect caused by a D/A-converter in an OFDM transmitter is presented. Practical implementations utilising very simple ramp generators are presented also. The method is tested through simulations and the results are compared with the conventional sine compensation method based on filtering.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130365448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Geometrical analysis of two-transistor circuits with more than three operating points 三个以上工作点的双晶体管电路的几何分析
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523057
M. Claus
{"title":"Geometrical analysis of two-transistor circuits with more than three operating points","authors":"M. Claus","doi":"10.1109/ECCTD.2005.1523057","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523057","url":null,"abstract":"This paper presents a new geometrical motivated approach to analyse resistive networks decomposable into two 3-pole subnetworks. Especially, networks composed of two MOSTs or BJTs that can have more than three operating points are analysed with this method. All results are verified additionally with a homotopy method realisable with standard circuit simulators.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123203560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
One method for FIR minimum-phase multiplier-free filter design based on cosine and RRS filters 一种基于余弦滤波器和RRS滤波器的FIR最小相位无乘法器滤波器设计方法
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523135
G. Jovanovic-Dolecek, V. Dolecek, I. Karabegović
{"title":"One method for FIR minimum-phase multiplier-free filter design based on cosine and RRS filters","authors":"G. Jovanovic-Dolecek, V. Dolecek, I. Karabegović","doi":"10.1109/ECCTD.2005.1523135","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523135","url":null,"abstract":"This paper presents one simple method for direct multiplier-free narrowband minimum-phase FIR filter design. The design is based on the minimum-phase filter specification. The designed filter is a cascade of recursive running sum (RRS) filters and cosine filters. The sharpening technique is used to improve the magnitude characteristic of the designed filter. We apply different modified sharpening polynomials to RRS and cosine filters. As a result, we obtain a less complex design that meets the desired minimum-phase specification. The Rouche's theorem is used to prove that a designed filter is a minimum phase.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"33 7-8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123341487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs 低压低功耗CMOS流水线adc的级位优化
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1522991
O. Adeniran, A. Demosthenous
{"title":"Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs","authors":"O. Adeniran, A. Demosthenous","doi":"10.1109/ECCTD.2005.1522991","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1522991","url":null,"abstract":"This paper attempts to theoretically determine the optimal number of bit-per-stage required for the CMOS low-voltage (V/sub supply/ < 2.5V/sub th/) radix-2 pipeline ADC architecture, with minimization of power dissipation and analog complexity as the overall goal. The design of a 1.5 V, 21 mW, 25 MS/s, 10-bit pipeline ADC is employed as reference. The results of the optimization analysis show that 2.5 bit-per-stage is the optimum for the 10-bit ADC design with digital error correction. This can also be generalized for any n-bit low-voltage pipeline ADC.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123357774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Accurate modeling and experimental validation of an injection-locked frequency divider 注入锁定分频器的精确建模和实验验证
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523147
D. O'Neill, David Bourke, Zhipeng Ye, Michael Peter Kennedy
{"title":"Accurate modeling and experimental validation of an injection-locked frequency divider","authors":"D. O'Neill, David Bourke, Zhipeng Ye, Michael Peter Kennedy","doi":"10.1109/ECCTD.2005.1523147","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523147","url":null,"abstract":"In recent years, as injection-locked frequency dividers (ILFD) have become more widely used, numerous papers have proposed contradictory models for the locking bandwidth of the dividers. This paper attempts to resolve this conflict through the creation of an accurate simplified model to predict the locking range of an IFLD. A simple novel method of enlarging the locking range is also presented. The results are verified experimentally.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116515092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Practical considerations on doughnut transistors design 甜甜圈晶体管设计的实际考虑
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. Pub Date : 2005-10-31 DOI: 10.1109/ECCTD.2005.1523098
P. López, M. Oberst, H. Neubauer, J. Hauer, D. Cabello
{"title":"Practical considerations on doughnut transistors design","authors":"P. López, M. Oberst, H. Neubauer, J. Hauer, D. Cabello","doi":"10.1109/ECCTD.2005.1523098","DOIUrl":"https://doi.org/10.1109/ECCTD.2005.1523098","url":null,"abstract":"For applications where speed is important and custom design is an option, doughnut transistors constitute an attractive alternative to standard topologies, efficiently reducing parasitic capacitances while keeping large W/L ratios. This paper explores the influence of the layout style on the chip performance. To this aim a two-stage op-amp where different types of doughnut layouts have been considered for the Input differential pair has been constructed and measured. Experimental results suggest better performance for circle-type layouts.","PeriodicalId":266120,"journal":{"name":"Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114707026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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