2006 7th Annual Non-Volatile Memory Technology Symposium最新文献_第2页

Switching Properties in Spin Transper Torque MRAM with sub-5Onm MTJ size MTJ尺寸小于5m的自旋转矩MRAM的开关特性

2006 7th Annual Non-Volatile Memory Technology Symposium Pub Date : 2006-11-01 DOI: 10.1109/NVMT.2006.378875

K. Nam, S.C. Oh, J. Lee, J. Jeong, I. Baek, E. Yim, J.S. Zhao, S.O. Park, H. Kim, U. Chung, J. Moon

引用次数: 16

Unique Challenges and Solutions in CMOS Compatible NVM CMOS兼容NVM的独特挑战和解决方案

2006 7th Annual Non-Volatile Memory Technology Symposium Pub Date : 2006-11-01 DOI: 10.1109/NVMT.2006.378876

J. Bu, W. Belcher, C. Parker, H. Prosack

引用次数: 2

Magnetic Shadow RAM 磁影内存

2006 7th Annual Non-Volatile Memory Technology Symposium Pub Date : 2006-11-01 DOI: 10.1109/NVMT.2006.378874

K. Hass, G. Donohoe, Y. Hong, B. Choi, K. DeGregorio, R. Hayhurst

引用次数: 11

Microstructure and resistance switching in NiO binary oxide films obtained from Ni oxidation 镍氧化制备的NiO二元氧化膜的微观结构和电阻开关

2006 7th Annual Non-Volatile Memory Technology Symposium Pub Date : 2006-11-01 DOI: 10.1109/NVMT.2006.378885

L. Courtade, C. Turquat, C. Muller, J. Lisoni, L. Goux, D. Wouters, D. Goguenheim

{"title":"Microstructure and resistance switching in NiO binary oxide films obtained from Ni oxidation","authors":"L. Courtade, C. Turquat, C. Muller, J. Lisoni, L. Goux, D. Wouters, D. Goguenheim","doi":"10.1109/NVMT.2006.378885","DOIUrl":"https://doi.org/10.1109/NVMT.2006.378885","url":null,"abstract":"Oxide Resistive Random Access Memories (OxRRAM) are discussed for future high density non volatile memory chips. NiO and other simple binary transition metal oxides (such as TiO2, HfO2 or ZrO2) have recently attracted much attention. In most cases, polycrystalline oxide films are deposited by reactive sputtering on conductive substrates to form bi-stable Metal/Resistive oxide/Metal (MRM) structures. In this paper, an alternative way is explored to obtain NiO films from the controlled oxidation of a Ni metallic film. Different thermal treatments were evaluated to oxidize the metallic film with conditions preventing the complete consumption of Ni film used as bottom electrode. Process parameters of Rapid Thermal Annealing (RTA) route were adjusted to achieve controlled oxidation. Microstructural and electrical analyzes were performed to apprehend the influence of the process parameters on the switching behavior. Reproducible resistive switching phenomena have been demonstrated in Pt/NiO/Ni structures with threshold voltage varying from 2 to 5 V depending on oxidizing conditions.","PeriodicalId":263387,"journal":{"name":"2006 7th Annual Non-Volatile Memory Technology Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125257226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Electrodeposit Formation in Solid Electrolytes 固体电解质中电沉积的形成

2006 7th Annual Non-Volatile Memory Technology Symposium Pub Date : 2006-11-01 DOI: 10.1109/NVMT.2006.378888

M. Kozicki, C. Ratnakumar, M. Mitkova

引用次数: 18

Visualization Using the Scanning Nonlinear Dielectric Microscopy of Electrons and Holes Localized in the Thin Gate Film of Metal-Oxide-Nitride-Oxide-Semiconductor Type Flash Memory 金属-氧化物-氮化物-半导体型快闪存储器薄膜中电子和空穴的扫描非线性介电显微镜可视化

2006 7th Annual Non-Volatile Memory Technology Symposium Pub Date : 2006-11-01 DOI: 10.1109/NVMT.2006.378866

K. Honda, Yasuo Cho

引用次数: 4

Eliminating Word Line Bending In Floating Gate NOR Flash Memory To Reduce Array Size and Improve Manufacturability 消除浮栅NOR快闪记忆体字线弯曲以减少阵列尺寸及提高制造性

2006 7th Annual Non-Volatile Memory Technology Symposium Pub Date : 2006-11-01 DOI: 10.1109/NVMT.2006.378869

S. Fang, Kuo-Tung Chang, Sung-Chul Lee, J. Reiss, M. Takahashi, M. Plat, S. Ho, A. Rangarajan, Wing Leung, M. Kwan, Sheung-Hee Park, K. Ko, A. Joshi, H. Kinoshita, J. Wang, Yu Sun, K. Mizutani, H. Ogawa

{"title":"Eliminating Word Line Bending In Floating Gate NOR Flash Memory To Reduce Array Size and Improve Manufacturability","authors":"S. Fang, Kuo-Tung Chang, Sung-Chul Lee, J. Reiss, M. Takahashi, M. Plat, S. Ho, A. Rangarajan, Wing Leung, M. Kwan, Sheung-Hee Park, K. Ko, A. Joshi, H. Kinoshita, J. Wang, Yu Sun, K. Mizutani, H. Ogawa","doi":"10.1109/NVMT.2006.378869","DOIUrl":"https://doi.org/10.1109/NVMT.2006.378869","url":null,"abstract":"In floating gate (FG) NOR flash memory arrays, word lines (WL) bend at Vss columns to accommodate the Vss contacts. As the memory cell is scaled down, patterning of the WL bending becomes more and more challenging. Furthermore, to ensure that the WL bending does not extend to the adjacent memory cells to cause abnormal electrical characteristics of the adjacent cells, we have to increase the Vss column width to three or more pitches. The wider Vss columns result in unequal line and spacing, which makes a significant impact on the process window of several modules. Therefore, the WL bending is a process limiter to core cell scaling and manufacturing. In this work, we have succeeded in a device approach to eliminate the WL bending by an additional mask and implant to connect Vss lines and contacts through conductive Vss transistors. The new memory array without WL bending shows comparable device performance and improves manufacturability significantly.","PeriodicalId":263387,"journal":{"name":"2006 7th Annual Non-Volatile Memory Technology Symposium","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134423078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Resistance Switching Characteristics of Metal Oxide and Schottky Junction for Nonvolatile Memory Applications 非易失性存储器用金属氧化物和肖特基结的电阻开关特性

2006 7th Annual Non-Volatile Memory Technology Symposium Pub Date : 2006-11-01 DOI: 10.1109/NVMT.2006.378884

Dongsoo Lee, W. Xiang, Dongjun Sung, R. Dong, Seokjoon Oh, Hyejung Choi, H. Hwang

{"title":"Resistance Switching Characteristics of Metal Oxide and Schottky Junction for Nonvolatile Memory Applications","authors":"Dongsoo Lee, W. Xiang, Dongjun Sung, R. Dong, Seokjoon Oh, Hyejung Choi, H. Hwang","doi":"10.1109/NVMT.2006.378884","DOIUrl":"https://doi.org/10.1109/NVMT.2006.378884","url":null,"abstract":"We evaluated the resistive switching effect of the polycrystalline oxide (Nb2O5, ZrOx and Cr-SrTiO3) fabricated by reactive sputtering and PLD. It shows a well-developed resistive switching behavior. The reproducible resistance switching cycles were observed and the resistance ratio was as high as 50~100 times. The resistance switching was observed under voltage pulse as short as 10 nsec. The estimated retention lifetime at 85degC was sufficiently longer than 10 years. However, we observed a significant non-uniformity of resistance switching behavior. To improve uniformity of resistance switching, we have investigated single crystal Nb-doped SrTiO3 in terms of its potential utility in nonvolatile memory applications. Compared with polycrystalline oxide (Nb2O5, ZrOx and Cr-doped SrTiO3), the Pt/single crystal Nb:SrTiO3 Schottky junction exhibits excellent memory characteristics including uniformity of set/reset bias, die-to-die reproducibility, data retention at high temperature, reliability under cycle stress, and multi-bit operation characteristics. Considering the area dependent resistance value and low temperature I-V characteristics, resistance switching might be explained by modulation of the Schottky barrier height by charge trapping and detrapping at the interface. In order to introduce Nb:SrTiO3 into CMOS process and reserve its excellent characteristics of single crystal, we deposited epitaxial Nb:SrTiO3 film on Si substrate using conducting TiN as a buffer layer. Based on XRD, RBS and TEM measurements, epitaxial growth of TiN and Nb:SrTiO3 films were confirmed. Moreover, the electrical and reliability properties of Pt/Nb:SrTiO3/TiN/Si structure are similar with that of Pt/single crystal Nb:SrTiO3 junction. Considering excellent uniformity and reproducibility of Pt/Nb:SrTiO3 Schottky junction, it shows good promise for future nonvolatile memory applications.","PeriodicalId":263387,"journal":{"name":"2006 7th Annual Non-Volatile Memory Technology Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132151365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Resistance Switching Memory Effect in Transition Metal Oxide Thin Films 过渡金属氧化物薄膜的电阻开关记忆效应

2006 7th Annual Non-Volatile Memory Technology Symposium Pub Date : 2006-11-01 DOI: 10.1109/NVMT.2006.378886

A. Ignatiev, N. Wu, S.Q. Liu, X. Chen, Y. Nian, C. Papaginanni, J. Strozier, Z. Xing

引用次数: 7

A New Self-Aligned NAND Type SONOS Flash Memory with High Scaling Abilities, Fast Programming/Erase Speeds and Good Data Retention Performances 一种新型自对准NAND型SONOS闪存，具有高缩放能力，快速编程/擦除速度和良好的数据保留性能

2006 7th Annual Non-Volatile Memory Technology Symposium Pub Date : 2006-11-01 DOI: 10.1109/NVMT.2006.378868

C. Kuo, E. Yang, W. Wong, C. Chao, Chih-Kai Kang, Li-Wei Liu, Tzung-Bin Huang, L. Kuo, Shi-Hsien Chen, Houng-Chi Wei, H. Hwang, S. Pittikoun

{"title":"A New Self-Aligned NAND Type SONOS Flash Memory with High Scaling Abilities, Fast Programming/Erase Speeds and Good Data Retention Performances","authors":"C. Kuo, E. Yang, W. Wong, C. Chao, Chih-Kai Kang, Li-Wei Liu, Tzung-Bin Huang, L. Kuo, Shi-Hsien Chen, Houng-Chi Wei, H. Hwang, S. Pittikoun","doi":"10.1109/NVMT.2006.378868","DOIUrl":"https://doi.org/10.1109/NVMT.2006.378868","url":null,"abstract":"In this paper, we will propose a new NAND type SONOS cell structure with high efficiency Source Side Injection programming and F-N erase. This cell is characterized in high scaling abilities, fast program/erase speeds and very satisfactory data retention performances. In consideration of the threshold voltage saturation of the SONOS cell during erase, we use the modified erase bias configuration, DSPE (decrement step pulse erase), to speed up the erase operation and enlarge the memory window without adding any process complexities. To further improve the erase speed, p+-poly gate has firstly been utilized on our NAND type SONOS cell. From our experimental results, p+-poly gate not only prolongs erase threshold voltage saturation to the longer time but improves charge loss characteristics. Instead of traditional threshold voltage extrapolations from short to long time, we applied the time constant model to predict concrete threshold voltage values with various baking time and temperatures.","PeriodicalId":263387,"journal":{"name":"2006 7th Annual Non-Volatile Memory Technology Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121035493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2