Unique Challenges and Solutions in CMOS Compatible NVM

Abstract

CMOS compatible NVM is finding increasing applications that range from a few bits in analog trim applications to kilobits for data or code. CMOS compatibility comes with unique retention and endurance challenges. The floating gate is in direct contact with backend dielectric, which degrades high temperature data retention performance. Drain and well doping profile are not optimized to favor hot carrier generation and injection. Endurance is poor due to serious oxide damage. Mechanisms and preferred solutions are described. Experiment results match theoretical analysis.