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Nanoelectronics devices: More CMOS, fusion CMOS and beyond CMOS 纳米电子器件:更多的CMOS，融合CMOS和超越CMOS
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357243
Hisatsune Watanabe
{"title":"Nanoelectronics devices: More CMOS, fusion CMOS and beyond CMOS","authors":"Hisatsune Watanabe","doi":"10.1109/ASSCC.2009.5357243","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357243","url":null,"abstract":"We are facing several difficulties with shrinking LSI chips, such as leakage currents/power consumption, variability, huge costs in R&D and production. Major semiconductor market will be absolutely dependent on further shrinking of Si CMOS transistors with improving transistor structures and lowering drive voltage, increasing wafer diameter and 3D stacking package structures. This way is “More CMOS” (More Moore) strategy. On the other hand, the semiconductor market will expand by integrating CMOS with new functional materials, such as optical-, flexible-, spin- mechanical-, bio-, and nano-carbon devices. This way is “Fusion CMOS”. “Beyond CMOS” circuit algorithm is intensively exploited mainly by academic sites. For acceleration of the commercialization of those R&D efforts for More CMOS, Fusion CMOS and Beyond CMOS, we need a new type of integration verification services for R&D people, particularly for university people. This might be a global need in the forthcoming nanoelectronics era.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131695860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An on-chip high-speed 4-bit BCH decoder in MLC NOR flash memories 一种用于MLC NOR闪存的片上高速4位BCH解码器
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357220
Xueqian Wang, Dong Wu, L. Pan, R. Zhou, Chaohong Hu
{"title":"An on-chip high-speed 4-bit BCH decoder in MLC NOR flash memories","authors":"Xueqian Wang, Dong Wu, L. Pan, R. Zhou, Chaohong Hu","doi":"10.1109/ASSCC.2009.5357220","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357220","url":null,"abstract":"An on-chip high-speed 4-bit BCH decoder for error correcting in a MLC NOR flash memory is presented. As process shrinking beyond 45nm, double-error-correcting (DEC) BCH code is needed for reliability requirement. A novel fastdecoding algorithm is developed by eliminating finite field divisions and combining arithmetic operations. As a result, the decoding latency is significantly reduced by 80%. Furthermore, a novel architecture of the 4-bit BCH decoder in a 2b/cell NOR flash memory is proposed to obtain a good time-area trade-off. Simulation results show that the latency of the 4-bit BCH decoder achieves only 6.4ns and satisfies fast access time of a NOR Flash memory.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132082360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A low-offset latched comparator using zero-static power dynamic offset cancellation technique 采用零静态功率动态偏移抵消技术的低偏置锁存比较器
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357221
M. Miyahara, A. Matsuzawa
{"title":"A low-offset latched comparator using zero-static power dynamic offset cancellation technique","authors":"M. Miyahara, A. Matsuzawa","doi":"10.1109/ASSCC.2009.5357221","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357221","url":null,"abstract":"A low-offset latched comparator using new dynamic offset cancellation technique is proposed. The new technique achieves low offset voltage without pre-amplifier and quiescent current. Furthermore the overdrive voltage of the input transistor can be optimized to reduce the offset voltage of the comparator independent of the input common mode voltage. A prototype comparator has been fabricated in 90 nm 9M1P CMOS technology with 152 µm2. Experimental results show that the comparator achieves 3.8 mV offset at 1 sigma at 500 MHz operating, while dissipating 39 μW from a 1.2 V supply.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"888 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131421050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 69
An on-chip continuous time power supply noise monitoring technique 一种片上连续时间电源噪声监测技术
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357188
Y. Bando, S. Takaya, M. Nagata
{"title":"An on-chip continuous time power supply noise monitoring technique","authors":"Y. Bando, S. Takaya, M. Nagata","doi":"10.1109/ASSCC.2009.5357188","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357188","url":null,"abstract":"A continuous-time power supply noise monitoring technique features a coverage of voltage domains at Vdd as well as at Vss and multi-channel probing at more than a hundred locations on power planes in a circuit. Methods toward quality on-chip power supply noise measurements are derived. A calibration flow eliminates the offset as well as gain errors among probing channels. A combined evaluation of on-chip measurements and off-chip circuit simulation precisely characterizes probing performance. In addition, consistency was ensured among noise waveforms captured by sampled-time precise digitization and by the proposed continuous-time monitoring. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with ± 200 mV at 1.2 and 0.0 V, respectively, with less than 3 mV offset voltages among 240 probing channels, and with the effective bandwidth of 1.0 GHz.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131508615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Low power embedded DRAM using 0.6V super retention mode with word line data mirroring 低功耗嵌入式DRAM采用0.6V超级保持模式，字行数据镜像
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357146
T. Iwai, Mariko Kaku, T. Miyazaki, H. Iwai, H. Takenaka, A. Suzuki, S. Miyano, M. Hamada
{"title":"Low power embedded DRAM using 0.6V super retention mode with word line data mirroring","authors":"T. Iwai, Mariko Kaku, T. Miyazaki, H. Iwai, H. Takenaka, A. Suzuki, S. Miyano, M. Hamada","doi":"10.1109/ASSCC.2009.5357146","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357146","url":null,"abstract":"An 88% reduction of refresh power of the 65nm embedded DRAM is achieved using Super Retention Mode (SRM) with Word Line Data Mirroring(WLDM). The retention time in Super Retention Mode is measured in the range of 0.55V to 1.2V. The minimum refresh power is obtained at 0.6V. The retention time of Super Retention Mode at 0.6V is extended by 4.1 times from that of conventional single cell operation at 1.2V. The transition time from normal mode to Super Retention Mode of 22.6μs is achieved with only 0.4% area penalty.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132248739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A WiMAX turbo decoder with tailbiting BIP architecture 一种具有尾部BIP结构的WiMAX涡轮解码器
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357175
H. Arai, N. Miyamoto, K. Kotani, H. Fujisawa, Takashi Ito
{"title":"A WiMAX turbo decoder with tailbiting BIP architecture","authors":"H. Arai, N. Miyamoto, K. Kotani, H. Fujisawa, Takashi Ito","doi":"10.1109/ASSCC.2009.5357175","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357175","url":null,"abstract":"In this paper, a tailbiting block-interleaved pipelining (BIP) architecture is proposed for high-throughput and energy efficient WiMAX turbo decoders. Conventional sliding window (SW) BIP turbo decoders suffer from many warm-up calculations and large memory size when the number of pipeline stages is increased. Instead of the SW, we combined the tailbiting method with BIP. Consequently, more than 50% of the warm-up calculation was reduced, and necessary memory size became constant. We have implemented a tailbiting BIP WiMAX turbo decoder with 4 pipeline stages in the area of 3.8 mm2 using a 0.18 μm CMOS technology. The chip achieves 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131146740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 8Gb/s/link, 6.5mW/Gb/s memory interface with bimodal request bus 8Gb/s链路，6.5mW/Gb/s内存接口，双峰请求总线
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357237
Ken Chang, Haechang Lee, Ting Wu, K. Kaviani, K. Prabhu, W. Beyene, Norman Chan, Catherine Chen, T. Chin, Alok Gupta, C. Madden, Mahabaleshwara, L. Raghavan, Jie Shen, Xudong Shi
{"title":"An 8Gb/s/link, 6.5mW/Gb/s memory interface with bimodal request bus","authors":"Ken Chang, Haechang Lee, Ting Wu, K. Kaviani, K. Prabhu, W. Beyene, Norman Chan, Catherine Chen, T. Chin, Alok Gupta, C. Madden, Mahabaleshwara, L. Raghavan, Jie Shen, Xudong Shi","doi":"10.1109/ASSCC.2009.5357237","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357237","url":null,"abstract":"An 8Gb/s/link power optimized controller memory interface is implemented in TSMC 40nm G CMOS process. It is composed of 32 differential data links to support 32GB/s payload. The bimodal drivers of the request bus enable support of both 12 bits of 2Gb/s/link single-ended RSL (Rambus Signaling Level) for existing XDRTM memory and 6 bits of 8Gb/s/link differential signaling for next generation XDR2TM memory. A 1-tap pre-emphasis transmitter equalizer and a source-degenerated linear receiver equalizer with offset trim are added on this controller interface to reduce signal swing and thus minimize power in both write and read directions. The measurement results show that with a 100mV swing (peak-to-peak single-ended) for the read and a 150mV swing for the write, the timing margin is greater than 0.25UI at a BER of 10-12 with real memory transactions. The measured power efficiency for the PHY is 6.5mW/Gb/s.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132304144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 65-nm on-chip multi-mode asynchronous local power supply unit for multi-power domain SoCs achieving fine grain DVS 一种65nm片上多模异步本地电源单元，用于实现细粒度分布式交换机的多功率域soc
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357187
M. Ichihashi, H. Lhermet, E. Beigné, F. Rothan, M. Belleville, A. Amara
{"title":"A 65-nm on-chip multi-mode asynchronous local power supply unit for multi-power domain SoCs achieving fine grain DVS","authors":"M. Ichihashi, H. Lhermet, E. Beigné, F. Rothan, M. Belleville, A. Amara","doi":"10.1109/ASSCC.2009.5357187","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357187","url":null,"abstract":"This paper discusses a local power supply unit designed for fine grain dynamic voltage scaling (DVS) in a multi-power domain SoC. The proposed power supply unit is fully compatible with an I/O library and adaptable to various logic module power needs. It delivers the module operating voltage, from 1.2 V to 0.6 V, according to predefined operating power modes and is equipped with the module power gating. The designed circuit requires five-I/O-pad pitch area in a 65-nm technology. The first test chip demonstrates that the maximum power efficiency is over 87% and the measured current consumption in stand-by mode is only 19 nA regardless of the connected module.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"428 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132387482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A gated ring oscillator based parallel-TDC system with digital resolution enhancement 一种增强数字分辨率的门控环振荡器并联tdc系统
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357178
Kameswaran Vengattaramane, J. Borremans, M. Steyaert, J. Craninckx
{"title":"A gated ring oscillator based parallel-TDC system with digital resolution enhancement","authors":"Kameswaran Vengattaramane, J. Borremans, M. Steyaert, J. Craninckx","doi":"10.1109/ASSCC.2009.5357178","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357178","url":null,"abstract":"A digital resolution enhancement technique for time-to-digital converters (TDC) is proposed. This involves a simultaneous multi-channel measurement of a time-interval with low-complexity TDCs of varying resolutions. The coarse outputs of each converter are then digitally post-processed to obtain a single result whose precision is much better than that of any individual converter. A prototype system with 8 channels is demonstrated in 90-nm CMOS. 45MS/s output of each channel is algorithmically combined to obtain over 2–3X improvement in the resolution in 4/6/8 channel modes. The chip occupies 0.3 mm2 and draws up to a maximum of 4 mA from a 1.2 V supply.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125121834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A method for realizing a fast response time for the output current change of a MOS current-mode buck DC-DC converter which utilizes a quadratic and vin-dependent compensation slope 一种利用二次型和vin相关的补偿斜率实现MOS电流型降压DC-DC变换器输出电流变化快速响应的方法
2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI: 10.1109/ASSCC.2009.5357163
T. Sai, Y. Sugimoto
{"title":"A method for realizing a fast response time for the output current change of a MOS current-mode buck DC-DC converter which utilizes a quadratic and vin-dependent compensation slope","authors":"T. Sai, Y. Sugimoto","doi":"10.1109/ASSCC.2009.5357163","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357163","url":null,"abstract":"In this study, a fast response time of less than 10 us has been realized for the sudden output current change between 220 mA and 20 mA of a MOS current-mode buck DC-DC converter which utilizes a quadratic and input-voltage-dependent compensation slope. By using a quadratic and input-voltage-dependent compensation slope, the frequency characteristics of the current feedback loop become constant, and the converter's overall frequency characteristics come to be determined by just adjusting the frequency characteristics in the voltage feedback loop. By changing the time constant in an error amplifier to manipulate the phase margin, the converter's output voltage change becomes small and its response time becomes fast. The test chip of a MOS current-mode buck DC-DC converter using a 0.35-um CMOS process and a 5 MHz clock realized a 40.8 mV output voltage change and a 7.2 us of the response time.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121365052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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