Nanoelectronics devices: More CMOS, fusion CMOS and beyond CMOS

Abstract

We are facing several difficulties with shrinking LSI chips, such as leakage currents/power consumption, variability, huge costs in R&D and production. Major semiconductor market will be absolutely dependent on further shrinking of Si CMOS transistors with improving transistor structures and lowering drive voltage, increasing wafer diameter and 3D stacking package structures. This way is “More CMOS” (More Moore) strategy. On the other hand, the semiconductor market will expand by integrating CMOS with new functional materials, such as optical-, flexible-, spin- mechanical-, bio-, and nano-carbon devices. This way is “Fusion CMOS”. “Beyond CMOS” circuit algorithm is intensively exploited mainly by academic sites. For acceleration of the commercialization of those R&D efforts for More CMOS, Fusion CMOS and Beyond CMOS, we need a new type of integration verification services for R&D people, particularly for university people. This might be a global need in the forthcoming nanoelectronics era.